[llvm] PPC: Fix regression for 32-bit ppc with 64-bit support (PR #159893)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/159893

Fixes regression after e5bbaa9c8fb6e06dbcbd39404039cc5d31df4410.
e5500 accidentally still had the 64bit feature applied instead of
64bit-support.

>From 8e93bc627475655f7bd32a7dd88dc0670cd1f8bf Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Sat, 20 Sep 2025 10:48:17 +0900
Subject: [PATCH] PPC: Fix regression for 32-bit ppc with 64-bit support

Fixes regression after e5bbaa9c8fb6e06dbcbd39404039cc5d31df4410.
e5500 accidentally still had the 64bit feature applied instead of
64bit-support.
---
 llvm/lib/Target/PowerPC/PPC.td                |  2 +-
 .../PowerPC/ppc32_64bit_support_cpus.ll       | 66 +++++++++++++++++++
 2 files changed, 67 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/PowerPC/ppc32_64bit_support_cpus.ll

diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index d491e88b66ad8..d89a9487c0da2 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -695,7 +695,7 @@ def : ProcessorModel<"e500mc", PPCE500mcModel,
                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
                    FeatureISEL, FeatureMFTB]>;
 def : ProcessorModel<"e5500", PPCE5500Model,
-                  [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
+                  [DirectiveE5500, FeatureMFOCRF, Feature64BitSupport,
                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
                    FeatureISEL, FeatureMFTB]>;
 def : ProcessorModel<"a2", PPCA2Model,
diff --git a/llvm/test/CodeGen/PowerPC/ppc32_64bit_support_cpus.ll b/llvm/test/CodeGen/PowerPC/ppc32_64bit_support_cpus.ll
new file mode 100644
index 0000000000000..d9ce9e663040d
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/ppc32_64bit_support_cpus.ll
@@ -0,0 +1,66 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=powerpc-unknown-linux-gnu -mcpu=e5500 < %s | FileCheck -check-prefix=PPC32 %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=e5500 < %s | FileCheck -check-prefix=PPC64 %s
+
+; Test that ppc32 triples work on cpus that support 64-bit.
+
+declare void @func(ptr)
+declare void @func_no_args()
+
+define void @call_assert() #0 {
+; PPC32-LABEL: call_assert:
+; PPC32:       # %bb.0:
+; PPC32-NEXT:    mflr 0
+; PPC32-NEXT:    stwu 1, -16(1)
+; PPC32-NEXT:    li 3, 0
+; PPC32-NEXT:    stw 0, 20(1)
+; PPC32-NEXT:    bl func
+; PPC32-NEXT:    lwz 0, 20(1)
+; PPC32-NEXT:    addi 1, 1, 16
+; PPC32-NEXT:    mtlr 0
+; PPC32-NEXT:    blr
+;
+; PPC64-LABEL: call_assert:
+; PPC64:       # %bb.0:
+; PPC64-NEXT:    mflr 0
+; PPC64-NEXT:    stdu 1, -112(1)
+; PPC64-NEXT:    li 3, 0
+; PPC64-NEXT:    std 0, 128(1)
+; PPC64-NEXT:    bl func
+; PPC64-NEXT:    nop
+; PPC64-NEXT:    addi 1, 1, 112
+; PPC64-NEXT:    ld 0, 16(1)
+; PPC64-NEXT:    mtlr 0
+; PPC64-NEXT:    blr
+  call void @func(ptr null)
+  ret void
+}
+
+define void @call_nop_select_fail() #0 {
+; PPC32-LABEL: call_nop_select_fail:
+; PPC32:       # %bb.0:
+; PPC32-NEXT:    mflr 0
+; PPC32-NEXT:    stwu 1, -16(1)
+; PPC32-NEXT:    stw 0, 20(1)
+; PPC32-NEXT:    bl func_no_args
+; PPC32-NEXT:    lwz 0, 20(1)
+; PPC32-NEXT:    addi 1, 1, 16
+; PPC32-NEXT:    mtlr 0
+; PPC32-NEXT:    blr
+;
+; PPC64-LABEL: call_nop_select_fail:
+; PPC64:       # %bb.0:
+; PPC64-NEXT:    mflr 0
+; PPC64-NEXT:    stdu 1, -112(1)
+; PPC64-NEXT:    std 0, 128(1)
+; PPC64-NEXT:    bl func_no_args
+; PPC64-NEXT:    nop
+; PPC64-NEXT:    addi 1, 1, 112
+; PPC64-NEXT:    ld 0, 16(1)
+; PPC64-NEXT:    mtlr 0
+; PPC64-NEXT:    blr
+  call void @func_no_args()
+  ret void
+}
+
+attributes #0 = { nounwind }