[llvm] [PowerPC] Implement AES Acceleration Instructions (PR #157725)

[Maryam Moghadas via llvm-commits]

================
@@ -120,6 +120,74 @@ class VXForm_VRTAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
   let Inst{21...31} = xo;
 }
 
+class XX3Form_XTBp5_M2<bits<9> xo, dag OOL, dag IOL, string asmstr,
+                       list<dag> pattern>
+    : I<60, OOL, IOL, asmstr, NoItinerary> {
+
+  bits<5> XTp;
+  bits<5> XBp;
+  bits<2> M;
+
+  let Pattern = pattern;
+
+  let Inst{6...9} = XTp{3...0};
+  let Inst {10} = XTp{4};
+  let Inst{15} = M{0};
+  let Inst{16...19} = XBp{3...0};
+  let Inst{20} = M{1};
+  let Inst{21...29} = xo;
+  let Inst{30} = XBp{4};
+}
+
+class XX3Form_XTABp5_M2<bits<8> xo, dag OOL, dag IOL, string asmstr,
+                        list<dag> pattern>
+    : I<60, OOL, IOL, asmstr, NoItinerary> {
+
+  bits<5> XTp;
+  bits<5> XAp;
+  bits<5> XBp;
+  bits<2> M;
+
+  let Pattern = pattern;
+
+  let Inst{6...9} = XTp{3...0};
+  let Inst{10} = XTp{4};
+  let Inst{11...14} = XAp{3...0};
+  let Inst{15} = M{0};
+  let Inst{16...19} = XBp{3...0};
+  let Inst{20} = M{1};
+  let Inst{21...28} = xo;
+  let Inst{29} = XAp{4};
+  let Inst{30} = XBp{4};
+}
+
+class XX3Form_XTAB6_P1<bits<5> xo, dag OOL, dag IOL, string asmstr,
+                       list<dag> pattern>
+    : I<60, OOL, IOL, asmstr, NoItinerary> {
+
+  bits<6> XT;
+  bits<6> XA;
+  bits<6> XB;
+  bits<1> P;
+
+  let Pattern = pattern;
+
+  let Inst{6...10} = XT{4...0};
+  let Inst{11...15} = XA{4...0};
+  let Inst{16...20} = XB{4...0};
+  let Inst{21...22} = 3;
+  let Inst{23} = P;
+  let Inst{24...28} = xo;
+  let Inst{29} = XA{5};
+  let Inst{30} = XB{5};
+  let Inst{31} = XT{5};
+}
+
+//-------------------------- Instruction definitions -------------------------//
+// Predicate combinations available:
+// [IsISAFuture]
+// [HasVSX, IsISAFuture]
----------------
maryammo wrote:

These AES instructions use VSX registers, so do we need HasVSX predicate? 

https://github.com/llvm/llvm-project/pull/157725