[llvm] added ISD::VECTOR_COMPRESS handling in computeKnownBits/ComputeNumSign… (PR #159692)

[Simon Pilgrim via llvm-commits]

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@@ -3480,6 +3481,26 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
         break;
     }
     break;
+  case ISD::VECTOR_COMPRESS: {
+    assert(!Op.getValueType().isScalableVector());
+
+    SDValue Vec = Op.getOperand(0);
+    SDValue PassThru = Op.getOperand(2);
+    // If PassThru is undefined, early out
+    if (PassThru.isUndef())
+      break;
+
+    Known.Zero.setAllBits();
+    Known.One.setAllBits();
+    Known2 = computeKnownBits(PassThru, Depth + 1);
+    Known = Known.intersectWith(Known2);
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RKSimon wrote:

also, can we use DemandedElts for the PassThru knownbits? AFAICT that will stay in the same elements if used?

https://github.com/llvm/llvm-project/pull/159692