[llvm] Greedy: Simplify collectHintInfo using MachineOperands. NFCI. (PR #159724)

[Jay Foad via llvm-commits]

https://github.com/jayfoad created https://github.com/llvm/llvm-project/pull/159724

If a COPY uses Reg but only in an implicit operand then the new
implementation ignores it but the old implementation would have treated
it as a copy of Reg. Probably this case never occurs in practice. Other
than that, this patch is NFC.


>From d2eaa29c04b65c06ae4f08e545fbab3a1c22a5f9 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Fri, 19 Sep 2025 09:47:35 +0100
Subject: [PATCH] Greedy: Simplify collectHintInfo using MachineOperands. NFCI.

If a COPY uses Reg but only in an implicit operand then the new
implementation ignores it but the old implementation would have treated
it as a copy of Reg. Probably this case never occurs in practice. Other
than that, this patch is NFC.
---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 22 +++++++++-------------
 1 file changed, 9 insertions(+), 13 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 7c8444fc93af4..cbfc16859aba4 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2389,22 +2389,18 @@ void RAGreedy::initializeCSRCost() {
 void RAGreedy::collectHintInfo(Register Reg, HintsInfo &Out) {
   const TargetRegisterClass *RC = MRI->getRegClass(Reg);
 
-  for (const MachineInstr &Instr : MRI->reg_nodbg_instructions(Reg)) {
-    if (!Instr.isCopy())
+  for (const MachineOperand &Opnd : MRI->reg_nodbg_operands(Reg)) {
+    const MachineInstr &Instr = *Opnd.getParent();
+    if (!Instr.isCopy() || Opnd.isImplicit())
       continue;
 
     // Look for the other end of the copy.
-    Register OtherReg = Instr.getOperand(0).getReg();
-    unsigned OtherSubReg = Instr.getOperand(0).getSubReg();
-    unsigned SubReg = Instr.getOperand(1).getSubReg();
-
-    if (OtherReg == Reg) {
-      OtherReg = Instr.getOperand(1).getReg();
-      OtherSubReg = Instr.getOperand(1).getSubReg();
-      SubReg = Instr.getOperand(0).getSubReg();
-      if (OtherReg == Reg)
-        continue;
-    }
+    const MachineOperand &OtherOpnd = Instr.getOperand(1 - Opnd.getOperandNo());
+    Register OtherReg = OtherOpnd.getReg();
+    if (OtherReg == Reg)
+      continue;
+    unsigned OtherSubReg = OtherOpnd.getSubReg();
+    unsigned SubReg = Opnd.getSubReg();
 
     // Get the current assignment.
     MCRegister OtherPhysReg =