[llvm] [RISCV]Do not combine to 'vw' if the number of extended instructions cannot be reduced (PR #159715)

[Liao Chunyu via llvm-commits]

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@@ -184,11 +181,10 @@ entry:
 define i32 @vdotqsu_vx_constant(<vscale x 16 x i8> %a) {
 ; CHECK-LABEL: vdotqsu_vx_constant:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT:    vsext.vf2 v16, v8
+; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT:    vsext.vf4 v16, v8
 ; CHECK-NEXT:    li a0, 123
-; CHECK-NEXT:    vwmul.vx v8, v16, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
+; CHECK-NEXT:    vmul.vx v8, v16, a0
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ChunyuLiao wrote:

I cross-compiled part SPEC CPU 2017 (since it can only be partially passed), and I will supplement the objdump results later.  if without increasing the number of spills, perhaps it could be considered good? 

https://github.com/llvm/llvm-project/pull/159715