[clang] [llvm] RISCV: the builtins support for MIPS RV64 P8700 execution control . (PR #159246)

[via llvm-commits]

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@@ -0,0 +1,35 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6
+// RUN: %clang_cc1 -triple riscv32-linux-elf -O3  -target-feature +xmipsexectl -emit-llvm -o - %s  | FileCheck %s
+
+// CHECK-LABEL: define dso_local void @test_mips_pause(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    tail call void @llvm.riscv.mips.pause()
+// CHECK-NEXT:    ret void
+//
+void test_mips_pause()
+{
+	__builtin_riscv_mips_pause();
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ukalappa-mips wrote:

Currently our GCC port ,doesn't have one ....but it always good to have ...

https://github.com/llvm/llvm-project/pull/159246