[llvm] dda7ce6 - [RISCV] Move Xqci Select-likes to use riscv_selectcc (#153147)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 18 17:16:48 PDT 2025
Author: Sam Elliott
Date: 2025-09-19T00:16:44Z
New Revision: dda7ce6624e357076fefe55a756ba7181db92ba2
URL: https://github.com/llvm/llvm-project/commit/dda7ce6624e357076fefe55a756ba7181db92ba2
DIFF: https://github.com/llvm/llvm-project/commit/dda7ce6624e357076fefe55a756ba7181db92ba2.diff
LOG: [RISCV] Move Xqci Select-likes to use riscv_selectcc (#153147)
The original patterns for the Xqci select-like instructions used
`select`, and marked that ISD node as legal. This is not the usual way
that `select` is dealt with in the RISC-V backend.
Usually on RISC-V, we expand `select` to `riscv_select_cc` which holds
references to the operands of the comparison and the possible values
depending on the comparison. In retrospect, this is a much better fit
for our instructions, as most of them correspond to specific condition
codes, rather than more generic `select` with a truthy/falsey value.
This PR moves the Xqci select-like patterns to use `riscv_select_cc`
nodes. This applies to the Xqcicm, Xqcics and Xqcicli instruction
patterns.
In order to match the existing codegen, minor additions had to be made
to `translateSetCCForBranch` to ensure that comparisons against specific
immediate values are left in a form that can be matched more closely by
the instructions. This prevents having to insert additional `li`
instructions and use the register forms.
There are a few slight regressions:
- There are sometimes more `mv` instructions than entirely necessary. I
believe these would not be seen with larger examples where the register
allocator has more leeway.
- In some tests where just one of the three extensions is enabled,
codegen falls back to using a branch over a move. With all three
extensions enabled (the configuration we most care about), these are not
seen.
- The generated patterns are very similar to each other - they have
similar complexity (7 or 8) and there are still overlaps. Sometimes the
choice between two instructions can be affected by the order of the
patterns in the tablegen file.
One other change is that Xqcicm instructions are prioritised over Xqcics
instructions where they have identical patterns. This is done because
one of the the Xqcicm instructions is compressible (`qc.mveqi`), while
none of the Xqcics instructions are.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
llvm/test/CodeGen/RISCV/select-bare.ll
llvm/test/CodeGen/RISCV/select-cc.ll
llvm/test/CodeGen/RISCV/select-cond.ll
llvm/test/CodeGen/RISCV/select-const.ll
llvm/test/CodeGen/RISCV/select.ll
llvm/test/CodeGen/RISCV/xqcicli.ll
llvm/test/CodeGen/RISCV/xqcicm.ll
llvm/test/CodeGen/RISCV/xqcics.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 95703e33926c5..d0d82695edc9c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1498,6 +1498,8 @@ def HasVendorXqcicm
: Predicate<"Subtarget->hasVendorXqcicm()">,
AssemblerPredicate<(all_of FeatureVendorXqcicm),
"'Xqcicm' (Qualcomm uC Conditional Move Extension)">;
+def NoVendorXqcicm
+ : Predicate<"!Subtarget->hasVendorXqcicm()">;
def FeatureVendorXqcics
: RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Select Extension">;
@@ -1505,11 +1507,6 @@ def HasVendorXqcics
: Predicate<"Subtarget->hasVendorXqcics()">,
AssemblerPredicate<(all_of FeatureVendorXqcics),
"'Xqcics' (Qualcomm uC Conditional Select Extension)">;
-def NoVendorXqcics
- : Predicate<"!Subtarget->hasVendorXqcics()">;
-
-def HasVendorXqcicsOrXqcicm
- : Predicate<"Subtarget->hasVendorXqcics() || Subtarget->hasVendorXqcicm()">;
def FeatureVendorXqcicsr
: RISCVExperimentalExtension<0, 4, "Qualcomm uC CSR Extension">;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 29c8e92e888b3..4f659471253a4 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -434,8 +434,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::ABS, MVT::i32, Custom);
}
- if (!Subtarget.useCCMovInsn() && !Subtarget.hasVendorXTHeadCondMov() &&
- !Subtarget.hasVendorXqcicm() && !Subtarget.hasVendorXqcics())
+ if (!Subtarget.useCCMovInsn() && !Subtarget.hasVendorXTHeadCondMov())
setOperationAction(ISD::SELECT, XLenVT, Custom);
if (Subtarget.hasVendorXqcia() && !Subtarget.is64Bit()) {
@@ -2506,6 +2505,14 @@ static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
CC = ISD::SETGE;
return;
}
+ if ((Subtarget.hasVendorXqcicm() || Subtarget.hasVendorXqcicli()) &&
+ C != INT64_MAX && isInt<5>(C + 1)) {
+ // We have a conditional move instruction for SETGE but not SETGT.
+ // Convert X > C to X >= C + 1, if (C + 1) is a 5-bit signed immediate.
+ RHS = DAG.getSignedConstant(C + 1, DL, RHS.getValueType());
+ CC = ISD::SETGE;
+ return;
+ }
if (Subtarget.hasVendorXqcibi() && C != INT64_MAX && isInt<16>(C + 1)) {
// We have a branch immediate instruction for SETGE but not SETGT.
// Convert X > C to X >= C + 1, if (C + 1) is a 16-bit signed immediate.
@@ -2524,6 +2531,14 @@ static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
}
break;
case ISD::SETUGT:
+ if ((Subtarget.hasVendorXqcicm() || Subtarget.hasVendorXqcicli()) &&
+ C != INT64_MAX && isUInt<5>(C + 1)) {
+ // We have a conditional move instruction for SETUGE but not SETUGT.
+ // Convert X > C to X >= C + 1, if (C + 1) is a 5-bit signed immediate.
+ RHS = DAG.getConstant(C + 1, DL, RHS.getValueType());
+ CC = ISD::SETUGE;
+ return;
+ }
if (Subtarget.hasVendorXqcibi() && C != INT64_MAX && isUInt<16>(C + 1)) {
// We have a branch immediate instruction for SETUGE but not SETUGT.
// Convert X > C to X >= C + 1, if (C + 1) is a 16-bit unsigned
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 69796a68ecd6e..808d9117a1746 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1343,51 +1343,51 @@ class QCScaledStPat<PatFrag StoreOp, RVInst Inst>
(Inst GPR:$rd, GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt)>;
class QCIMVCCPat<CondCode Cond, QCIMVCC Inst>
- : Pat<(select (i32 (setcc (i32 GPRNoX0:$rs1), (i32 GPRNoX0:$rs2), Cond)), (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd)),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), (i32 GPRNoX0:$rs2), Cond, (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd))),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs3)>;
class QCIMVCCIPat<CondCode Cond, QCIMVCCI Inst, DAGOperand InTyImm>
- : Pat<(select (i32 (setcc (i32 GPRNoX0:$rs1), InTyImm:$imm, Cond)), (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd)),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), InTyImm:$imm, Cond, (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd))),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, InTyImm:$imm, GPRNoX0:$rs3)>;
class QCISELECTCCIPat<CondCode Cond, QCISELECTCCI Inst>
- : Pat<(select (i32 (setcc (i32 GPRNoX0:$rd), simm5:$imm, Cond)), (i32 GPRNoX0:$rs2), (i32 GPRNoX0:$rs3)),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), simm5:$imm, Cond, (i32 GPRNoX0:$rs2), (i32 GPRNoX0:$rs3))),
(Inst GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, GPRNoX0:$rs3)>;
class QCISELECTICCIPat<CondCode Cond, QCISELECTICCI Inst>
- : Pat<(select (i32 (setcc (i32 GPRNoX0:$rd), simm5:$imm, Cond)), (i32 GPRNoX0:$rs2), simm5:$simm2),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), simm5:$imm, Cond, (i32 GPRNoX0:$rs2), simm5:$simm2)),
(Inst GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, simm5:$simm2)>;
class QCISELECTICCIPatInv<CondCode Cond, QCISELECTICCI Inst>
- : Pat<(select (i32 (setcc (i32 GPRNoX0:$rd), simm5:$imm, Cond)), simm5:$simm2, (i32 GPRNoX0:$rs2)),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), simm5:$imm, Cond, simm5:$simm2, (i32 GPRNoX0:$rs2))),
(Inst GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, simm5:$simm2)>;
class QCISELECTICCPat<CondCode Cond, QCISELECTICC Inst>
- : Pat<(select (i32 (setcc (i32 GPRNoX0:$rd), (i32 GPRNoX0:$rs1), Cond)), (i32 GPRNoX0:$rs2), simm5:$simm2),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 GPRNoX0:$rs1), Cond, (i32 GPRNoX0:$rs2), simm5:$simm2)),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm2)>;
class QCISELECTICCPatInv<CondCode Cond, QCISELECTICC Inst>
- : Pat<(select (i32 (setcc (i32 GPRNoX0:$rd), (i32 GPRNoX0:$rs1), Cond)), simm5:$simm2, (i32 GPRNoX0:$rs2)),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 GPRNoX0:$rs1), Cond, simm5:$simm2, (i32 GPRNoX0:$rs2))),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm2)>;
class QCISELECTIICCPat<CondCode Cond, QCISELECTIICC Inst>
- : Pat<(select (i32 (setcc (i32 GPRNoX0:$rd), (i32 GPRNoX0:$rs1), Cond)), simm5:$simm1, simm5:$simm2),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 GPRNoX0:$rs1), Cond, simm5:$simm1, simm5:$simm2)),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, simm5:$simm1, simm5:$simm2)>;
class QCILICCPat<CondCode Cond, QCILICC Inst>
- : Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rs1), (XLenVT GPRNoX0:$rs2), Cond)), simm5:$simm, (XLenVT GPRNoX0:$rd)),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), (i32 GPRNoX0:$rs2), Cond, simm5:$simm, (i32 GPRNoX0:$rd))),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm)>;
class QCILICCPatInv<CondCode Cond, QCILICC Inst>
- : Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rs1), (XLenVT GPRNoX0:$rs2), Cond)), (XLenVT GPRNoX0:$rd), simm5:$simm),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), (i32 GPRNoX0:$rs2), Cond, (i32 GPRNoX0:$rd), simm5:$simm)),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm)>;
class QCILICCIPat<CondCode Cond, QCILICC Inst, DAGOperand InTyImm>
- : Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rs1), InTyImm:$imm, Cond)), simm5:$simm, (XLenVT GPRNoX0:$rd)),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), InTyImm:$imm, Cond, simm5:$simm, (i32 GPRNoX0:$rd))),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, InTyImm:$imm, simm5:$simm)>;
class QCILICCIPatInv<CondCode Cond, QCILICC Inst, DAGOperand InTyImm>
- : Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rs1), InTyImm:$imm, Cond)), (XLenVT GPRNoX0:$rd), simm5:$simm),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), InTyImm:$imm, Cond, (i32 GPRNoX0:$rd), simm5:$simm)),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, InTyImm:$imm, simm5:$simm)>;
// Match `riscv_brcc` and lower to the appropriate XQCIBI branch instruction.
@@ -1539,81 +1539,93 @@ let Predicates = [HasVendorXqciint, IsRV32] in
def : Pat<(riscv_mileaveret_glue), (QC_C_MILEAVERET)>;
let Predicates = [HasVendorXqcicm, IsRV32] in {
-def : Pat<(select (i32 GPRNoX0:$rs1), (i32 GPRNoX0:$rd),(i32 GPRNoX0:$rs3)),
- (QC_MVEQI GPRNoX0:$rd, GPRNoX0:$rs1, (i32 0), GPRNoX0:$rs3)>;
-
-def : QCIMVCCPat <SETEQ, QC_MVEQ>;
-def : QCIMVCCPat <SETNE, QC_MVNE>;
-def : QCIMVCCPat <SETLT, QC_MVLT>;
-def : QCIMVCCPat <SETULT, QC_MVLTU>;
-
-def : QCIMVCCIPat <SETLT, QC_MVLTI, simm5>;
-def : QCIMVCCIPat <SETULT, QC_MVLTUI, uimm5>;
-}
-
-// Prioritize Xqcics over these patterns.
-let Predicates = [HasVendorXqcicm, NoVendorXqcics, IsRV32] in {
-def : QCIMVCCIPat <SETEQ, QC_MVEQI, simm5>;
-def : QCIMVCCIPat <SETNE, QC_MVNEI, simm5>;
+// (SELECT X, Y, Z) is canonicalised to `(riscv_selectcc x, 0, NE, y, z)`.
+// This exists to prioritise over the `Select_GPR_Using_CC_GPR` pattern.
+def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), (i32 0), SETNE, (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd))),
+ (QC_MVNEI GPRNoX0:$rd, GPRNoX0:$rs1, 0, GPRNoX0:$rs3)>;
+def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), (i32 0), SETEQ, (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd))),
+ (QC_MVEQI GPRNoX0:$rd, GPRNoX0:$rs1, 0, GPRNoX0:$rs3)>;
+
+def : QCIMVCCPat<SETEQ, QC_MVEQ>;
+def : QCIMVCCPat<SETNE, QC_MVNE>;
+def : QCIMVCCPat<SETLT, QC_MVLT>;
+def : QCIMVCCPat<SETULT, QC_MVLTU>;
+def : QCIMVCCPat<SETGE, QC_MVGE>;
+def : QCIMVCCPat<SETUGE, QC_MVGEU>;
+
+def : QCIMVCCIPat<SETEQ, QC_MVEQI, simm5>;
+def : QCIMVCCIPat<SETNE, QC_MVNEI, simm5>;
+def : QCIMVCCIPat<SETLT, QC_MVLTI, simm5>;
+def : QCIMVCCIPat<SETULT, QC_MVLTUI, uimm5>;
+def : QCIMVCCIPat<SETGE, QC_MVGEI, simm5>;
+def : QCIMVCCIPat<SETUGE, QC_MVGEUI, uimm5>;
}
-let Predicates = [HasVendorXqcicli, HasVendorXqcicsOrXqcicm, IsRV32] in {
-def : QCILICCPat <SETEQ, QC_LIEQ>;
-def : QCILICCPat <SETNE, QC_LINE>;
-def : QCILICCPat <SETLT, QC_LILT>;
-def : QCILICCPat <SETGE, QC_LIGE>;
-def : QCILICCPat <SETULT, QC_LILTU>;
-def : QCILICCPat <SETUGE, QC_LIGEU>;
-
-def : QCILICCIPat <SETEQ, QC_LIEQI, simm5>;
-def : QCILICCIPat <SETNE, QC_LINEI, simm5>;
-def : QCILICCIPat <SETLT, QC_LILTI, simm5>;
-def : QCILICCIPat <SETGE, QC_LIGEI, simm5>;
-def : QCILICCIPat <SETULT, QC_LILTUI, uimm5>;
-def : QCILICCIPat <SETUGE, QC_LIGEUI, uimm5>;
-
-def : QCILICCPatInv <SETNE, QC_LIEQ>;
-def : QCILICCPatInv <SETEQ, QC_LINE>;
-def : QCILICCPatInv <SETGE, QC_LILT>;
-def : QCILICCPatInv <SETLT, QC_LIGE>;
-def : QCILICCPatInv <SETUGE, QC_LILTU>;
-def : QCILICCPatInv <SETULT, QC_LIGEU>;
-
-def : QCILICCIPatInv <SETNE, QC_LIEQI, simm5>;
-def : QCILICCIPatInv <SETEQ, QC_LINEI, simm5>;
-def : QCILICCIPatInv <SETGE, QC_LILTI, simm5>;
-def : QCILICCIPatInv <SETLT, QC_LIGEI, simm5>;
-def : QCILICCIPatInv <SETUGE, QC_LILTUI, uimm5>;
-def : QCILICCIPatInv <SETULT, QC_LIGEUI, uimm5>;
-}
+let Predicates = [HasVendorXqcicli, IsRV32] in {
+def : QCILICCPat<SETEQ, QC_LIEQ>;
+def : QCILICCPat<SETNE, QC_LINE>;
+def : QCILICCPat<SETLT, QC_LILT>;
+def : QCILICCPat<SETGE, QC_LIGE>;
+def : QCILICCPat<SETULT, QC_LILTU>;
+def : QCILICCPat<SETUGE, QC_LIGEU>;
+
+def : QCILICCIPat<SETEQ, QC_LIEQI, simm5>;
+def : QCILICCIPat<SETNE, QC_LINEI, simm5>;
+def : QCILICCIPat<SETLT, QC_LILTI, simm5>;
+def : QCILICCIPat<SETGE, QC_LIGEI, simm5>;
+def : QCILICCIPat<SETULT, QC_LILTUI, uimm5>;
+def : QCILICCIPat<SETUGE, QC_LIGEUI, uimm5>;
+
+def : QCILICCPatInv<SETNE, QC_LIEQ>;
+def : QCILICCPatInv<SETEQ, QC_LINE>;
+def : QCILICCPatInv<SETGE, QC_LILT>;
+def : QCILICCPatInv<SETLT, QC_LIGE>;
+def : QCILICCPatInv<SETUGE, QC_LILTU>;
+def : QCILICCPatInv<SETULT, QC_LIGEU>;
+
+def : QCILICCIPatInv<SETNE, QC_LIEQI, simm5>;
+def : QCILICCIPatInv<SETEQ, QC_LINEI, simm5>;
+def : QCILICCIPatInv<SETGE, QC_LILTI, simm5>;
+def : QCILICCIPatInv<SETLT, QC_LIGEI, simm5>;
+def : QCILICCIPatInv<SETUGE, QC_LILTUI, uimm5>;
+def : QCILICCIPatInv<SETULT, QC_LIGEUI, uimm5>;
+} // Predicates = [HasVendorXqcicli, IsRV32]
let Predicates = [HasVendorXqcics, IsRV32] in {
-def : Pat<(select (i32 GPRNoX0:$rd), (i32 GPRNoX0:$rs2),(i32 GPRNoX0:$rs3)),
- (QC_SELECTNEI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, GPRNoX0:$rs3)>;
-def : Pat<(select (i32 GPRNoX0:$rd), (i32 GPRNoX0:$rs2), simm5:$simm2),
+// (SELECT X, Y, Z) is canonicalised to `(riscv_selectcc x, 0, NE, y, z)`.
+// These exist to prioritise over the `Select_GPR_Using_CC_GPR` pattern.
+def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 0), SETNE, (i32 GPRNoX0:$rs2), simm5:$simm2)),
(QC_SELECTINEI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, simm5:$simm2)>;
-def : Pat<(select (i32 GPRNoX0:$rd), simm5:$simm2,(i32 GPRNoX0:$rs2)),
+def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 0), SETNE, simm5:$simm2, (i32 GPRNoX0:$rs2))),
(QC_SELECTIEQI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, simm5:$simm2)>;
-def : QCISELECTCCIPat <SETEQ, QC_SELECTEQI>;
-def : QCISELECTCCIPat <SETNE, QC_SELECTNEI>;
-
-def : QCISELECTICCIPat <SETEQ, QC_SELECTIEQI>;
-def : QCISELECTICCIPat <SETNE, QC_SELECTINEI>;
+def : QCISELECTICCIPat<SETEQ, QC_SELECTIEQI>;
+def : QCISELECTICCIPat<SETNE, QC_SELECTINEI>;
-def : QCISELECTICCIPatInv <SETEQ, QC_SELECTINEI>;
-def : QCISELECTICCIPatInv <SETNE, QC_SELECTIEQI>;
+def : QCISELECTICCIPatInv<SETEQ, QC_SELECTINEI>;
+def : QCISELECTICCIPatInv<SETNE, QC_SELECTIEQI>;
-def : QCISELECTICCPat <SETEQ, QC_SELECTIEQ>;
-def : QCISELECTICCPat <SETNE, QC_SELECTINE>;
+def : QCISELECTICCPat<SETEQ, QC_SELECTIEQ>;
+def : QCISELECTICCPat<SETNE, QC_SELECTINE>;
-def : QCISELECTICCPatInv <SETEQ, QC_SELECTINE>;
-def : QCISELECTICCPatInv <SETNE, QC_SELECTIEQ>;
+def : QCISELECTICCPatInv<SETEQ, QC_SELECTINE>;
+def : QCISELECTICCPatInv<SETNE, QC_SELECTIEQ>;
-def : QCISELECTIICCPat <SETEQ, QC_SELECTIIEQ>;
-def : QCISELECTIICCPat <SETNE, QC_SELECTIINE>;
+def : QCISELECTIICCPat<SETEQ, QC_SELECTIIEQ>;
+def : QCISELECTIICCPat<SETNE, QC_SELECTIINE>;
} // Predicates = [HasVendorXqcics, IsRV32]
+// Prioritize Xqcicm over these patterns, because Xqcicm is compressible.
+let Predicates = [HasVendorXqcics, NoVendorXqcicm, IsRV32] in {
+def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 0), SETNE, (i32 GPRNoX0:$rs2), (i32 GPRNoX0:$rs3))),
+ (QC_SELECTNEI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, GPRNoX0:$rs3)>;
+def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 0), SETEQ, (i32 GPRNoX0:$rs2), (i32 GPRNoX0:$rs3))),
+ (QC_SELECTEQI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, GPRNoX0:$rs3)>;
+
+def : QCISELECTCCIPat<SETEQ, QC_SELECTEQI>;
+def : QCISELECTCCIPat<SETNE, QC_SELECTNEI>;
+}
+
let Predicates = [HasVendorXqcilsm, IsRV32] in {
def : Pat<(qc_setwmi GPR:$rs3, GPR:$rs1, tuimm5nonzero:$uimm5, tuimm7_lsb00:$uimm7),
(QC_SETWMI GPR:$rs3, GPR:$rs1, tuimm5nonzero:$uimm5, tuimm7_lsb00:$uimm7)>;
diff --git a/llvm/test/CodeGen/RISCV/select-bare.ll b/llvm/test/CodeGen/RISCV/select-bare.ll
index fc8eaa480b116..796121ac572ce 100644
--- a/llvm/test/CodeGen/RISCV/select-bare.ll
+++ b/llvm/test/CodeGen/RISCV/select-bare.ll
@@ -3,6 +3,8 @@
; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: bare_select:
@@ -20,6 +22,13 @@ define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
; RV64I-CCMOV-NEXT: andi a0, a0, 1
; RV64I-CCMOV-NEXT: mips.ccmov a0, a0, a1, a2
; RV64I-CCMOV-NEXT: ret
+;
+; RV32IXQCI-LABEL: bare_select:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
%1 = select i1 %a, i32 %b, i32 %c
ret i32 %1
}
@@ -40,6 +49,13 @@ define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
; RV64I-CCMOV-NEXT: andi a0, a0, 1
; RV64I-CCMOV-NEXT: mips.ccmov a0, a0, a1, a2
; RV64I-CCMOV-NEXT: ret
+;
+; RV32IXQCI-LABEL: bare_select_float:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
%1 = select i1 %a, float %b, float %c
ret float %1
}
diff --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll
index 3df07073e0ed3..14055dff40d42 100644
--- a/llvm/test/CodeGen/RISCV/select-cc.ll
+++ b/llvm/test/CodeGen/RISCV/select-cc.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32I %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
; RUN: llc -mtriple=riscv64 -disable-block-placement -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \
@@ -83,6 +85,44 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind {
; RV32I-NEXT: .LBB0_28:
; RV32I-NEXT: ret
;
+; RV32IXQCI-LABEL: foo:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: lw a5, 0(a1)
+; RV32IXQCI-NEXT: lw a2, 0(a1)
+; RV32IXQCI-NEXT: lw a4, 0(a1)
+; RV32IXQCI-NEXT: lw t5, 0(a1)
+; RV32IXQCI-NEXT: lw t4, 0(a1)
+; RV32IXQCI-NEXT: lw t2, 0(a1)
+; RV32IXQCI-NEXT: lw t1, 0(a1)
+; RV32IXQCI-NEXT: lw t0, 0(a1)
+; RV32IXQCI-NEXT: lw a7, 0(a1)
+; RV32IXQCI-NEXT: lw a6, 0(a1)
+; RV32IXQCI-NEXT: lw t3, 0(a1)
+; RV32IXQCI-NEXT: lw a3, 0(a1)
+; RV32IXQCI-NEXT: bltz t3, .LBB0_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: li t6, 0
+; RV32IXQCI-NEXT: qc.mveq a5, a0, a5, a0
+; RV32IXQCI-NEXT: qc.mvne a2, a5, a2, a5
+; RV32IXQCI-NEXT: qc.mvltu a4, a4, a2, a2
+; RV32IXQCI-NEXT: qc.mvgeu t5, a4, t5, a4
+; RV32IXQCI-NEXT: qc.mvltu t4, t5, t4, t5
+; RV32IXQCI-NEXT: qc.mvgeu t2, t2, t4, t4
+; RV32IXQCI-NEXT: qc.mvlt t1, t1, t2, t2
+; RV32IXQCI-NEXT: qc.mvge t0, t1, t0, t1
+; RV32IXQCI-NEXT: qc.mvlt a7, t0, a7, t0
+; RV32IXQCI-NEXT: qc.mvge a6, a6, a7, a7
+; RV32IXQCI-NEXT: mv a3, t3
+; RV32IXQCI-NEXT: qc.mvge a3, t6, t3, a6
+; RV32IXQCI-NEXT: .LBB0_2:
+; RV32IXQCI-NEXT: lw a2, 0(a1)
+; RV32IXQCI-NEXT: lw a0, 0(a1)
+; RV32IXQCI-NEXT: li a1, 1024
+; RV32IXQCI-NEXT: qc.mvlt a2, a1, a2, a3
+; RV32IXQCI-NEXT: li a1, 2046
+; RV32IXQCI-NEXT: qc.mvltu a0, a1, t3, a2
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: foo:
; RV64I: # %bb.0:
; RV64I-NEXT: lw a2, 0(a1)
@@ -291,6 +331,24 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2,
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32IXQCI-LABEL: numsignbits:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: addi sp, sp, -16
+; RV32IXQCI-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IXQCI-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IXQCI-NEXT: mv s0, a2
+; RV32IXQCI-NEXT: qc.mveqi s0, a0, 0, a3
+; RV32IXQCI-NEXT: beqz a1, .LBB1_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: mv a0, s0
+; RV32IXQCI-NEXT: call bar
+; RV32IXQCI-NEXT: .LBB1_2:
+; RV32IXQCI-NEXT: mv a0, s0
+; RV32IXQCI-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IXQCI-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IXQCI-NEXT: addi sp, sp, 16
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: numsignbits:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -355,6 +413,14 @@ define i32 @select_sge_int16min(i32 signext %x, i32 signext %y, i32 signext %z)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret
;
+; RV32IXQCI-LABEL: select_sge_int16min:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: lui a3, 1048560
+; RV32IXQCI-NEXT: addi a3, a3, -1
+; RV32IXQCI-NEXT: qc.mvlt a2, a3, a0, a1
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: select_sge_int16min:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a3, 1048560
@@ -399,6 +465,18 @@ define i64 @select_sge_int32min(i64 %x, i64 %y, i64 %z) {
; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: ret
;
+; RV32IXQCI-LABEL: select_sge_int32min:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: srli a6, a0, 31
+; RV32IXQCI-NEXT: srli a0, a1, 31
+; RV32IXQCI-NEXT: xori a0, a0, 1
+; RV32IXQCI-NEXT: qc.mveqi a0, a1, -1, a6
+; RV32IXQCI-NEXT: qc.mvnei a4, a0, 0, a2
+; RV32IXQCI-NEXT: qc.mvnei a5, a0, 0, a3
+; RV32IXQCI-NEXT: mv a0, a4
+; RV32IXQCI-NEXT: mv a1, a5
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: select_sge_int32min:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a3, 524288
diff --git a/llvm/test/CodeGen/RISCV/select-cond.ll b/llvm/test/CodeGen/RISCV/select-cond.ll
index 59f4d95f45acc..b88fe9aae18ec 100644
--- a/llvm/test/CodeGen/RISCV/select-cond.ll
+++ b/llvm/test/CodeGen/RISCV/select-cond.ll
@@ -7,6 +7,8 @@
; RUN: | FileCheck %s --check-prefixes=RV32-XQCICM
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32-XQCICS
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV64
; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \
@@ -33,8 +35,8 @@ define signext i32 @select_i32_trunc(i32 signext %cond, i32 signext %x, i32 sign
; RV32-XQCICM-LABEL: select_i32_trunc:
; RV32-XQCICM: # %bb.0:
; RV32-XQCICM-NEXT: andi a0, a0, 1
-; RV32-XQCICM-NEXT: qc.mveqi a1, a0, 0, a2
-; RV32-XQCICM-NEXT: mv a0, a1
+; RV32-XQCICM-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_trunc:
@@ -43,6 +45,13 @@ define signext i32 @select_i32_trunc(i32 signext %cond, i32 signext %x, i32 sign
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_trunc:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_trunc:
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
@@ -84,8 +93,8 @@ define signext i32 @select_i32_param(i1 signext %cond, i32 signext %x, i32 signe
; RV32-XQCICM-LABEL: select_i32_param:
; RV32-XQCICM: # %bb.0:
; RV32-XQCICM-NEXT: andi a0, a0, 1
-; RV32-XQCICM-NEXT: qc.mveqi a1, a0, 0, a2
-; RV32-XQCICM-NEXT: mv a0, a1
+; RV32-XQCICM-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_param:
@@ -94,6 +103,13 @@ define signext i32 @select_i32_param(i1 signext %cond, i32 signext %x, i32 signe
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_param:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_param:
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
@@ -138,11 +154,19 @@ define signext i32 @select_i32_eq(i32 signext %a, i32 signext %b, i32 signext %x
;
; RV32-XQCICS-LABEL: select_i32_eq:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: xor a0, a0, a1
-; RV32-XQCICS-NEXT: seqz a0, a0
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
+; RV32-XQCICS-NEXT: beq a0, a1, .LBB2_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB2_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_eq:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mveq a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_eq:
; RV64: # %bb.0:
; RV64-NEXT: beq a0, a1, .LBB2_2
@@ -187,11 +211,19 @@ define signext i32 @select_i32_ne(i32 signext %a, i32 signext %b, i32 signext %x
;
; RV32-XQCICS-LABEL: select_i32_ne:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: xor a0, a0, a1
-; RV32-XQCICS-NEXT: snez a0, a0
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
+; RV32-XQCICS-NEXT: bne a0, a1, .LBB3_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB3_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_ne:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvne a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_ne:
; RV64: # %bb.0:
; RV64-NEXT: bne a0, a1, .LBB3_2
@@ -236,10 +268,19 @@ define signext i32 @select_i32_ugt(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICS-LABEL: select_i32_ugt:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: sltu a0, a1, a0
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
+; RV32-XQCICS-NEXT: bltu a1, a0, .LBB4_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB4_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_ugt:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvltu a3, a1, a0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_ugt:
; RV64: # %bb.0:
; RV64-NEXT: bltu a1, a0, .LBB4_2
@@ -278,16 +319,25 @@ define signext i32 @select_i32_uge(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_uge:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mvltu a2, a0, a1, a3
-; RV32-XQCICM-NEXT: mv a0, a2
+; RV32-XQCICM-NEXT: qc.mvgeu a3, a0, a1, a2
+; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_uge:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: sltu a0, a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a3, a2
+; RV32-XQCICS-NEXT: bgeu a0, a1, .LBB5_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB5_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_uge:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvgeu a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_uge:
; RV64: # %bb.0:
; RV64-NEXT: bgeu a0, a1, .LBB5_2
@@ -332,10 +382,19 @@ define signext i32 @select_i32_ult(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICS-LABEL: select_i32_ult:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: sltu a0, a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
+; RV32-XQCICS-NEXT: bltu a0, a1, .LBB6_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB6_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_ult:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvltu a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_ult:
; RV64: # %bb.0:
; RV64-NEXT: bltu a0, a1, .LBB6_2
@@ -374,16 +433,25 @@ define signext i32 @select_i32_ule(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_ule:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mvltu a2, a1, a0, a3
-; RV32-XQCICM-NEXT: mv a0, a2
+; RV32-XQCICM-NEXT: qc.mvgeu a3, a1, a0, a2
+; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_ule:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: sltu a0, a1, a0
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a3, a2
+; RV32-XQCICS-NEXT: bgeu a1, a0, .LBB7_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB7_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_ule:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvgeu a3, a1, a0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_ule:
; RV64: # %bb.0:
; RV64-NEXT: bgeu a1, a0, .LBB7_2
@@ -428,10 +496,19 @@ define signext i32 @select_i32_sgt(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICS-LABEL: select_i32_sgt:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: slt a0, a1, a0
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
+; RV32-XQCICS-NEXT: blt a1, a0, .LBB8_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB8_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_sgt:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvlt a3, a1, a0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_sgt:
; RV64: # %bb.0:
; RV64-NEXT: blt a1, a0, .LBB8_2
@@ -470,16 +547,25 @@ define signext i32 @select_i32_sge(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_sge:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mvlt a2, a0, a1, a3
-; RV32-XQCICM-NEXT: mv a0, a2
+; RV32-XQCICM-NEXT: qc.mvge a3, a0, a1, a2
+; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_sge:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: slt a0, a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a3, a2
+; RV32-XQCICS-NEXT: bge a0, a1, .LBB9_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB9_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_sge:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvge a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_sge:
; RV64: # %bb.0:
; RV64-NEXT: bge a0, a1, .LBB9_2
@@ -524,10 +610,19 @@ define signext i32 @select_i32_slt(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICS-LABEL: select_i32_slt:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: slt a0, a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
+; RV32-XQCICS-NEXT: blt a0, a1, .LBB10_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB10_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_slt:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvlt a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_slt:
; RV64: # %bb.0:
; RV64-NEXT: blt a0, a1, .LBB10_2
@@ -566,16 +661,25 @@ define signext i32 @select_i32_sle(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_sle:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mvlt a2, a1, a0, a3
-; RV32-XQCICM-NEXT: mv a0, a2
+; RV32-XQCICM-NEXT: qc.mvge a3, a1, a0, a2
+; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_sle:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: slt a0, a1, a0
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a3, a2
+; RV32-XQCICS-NEXT: bge a1, a0, .LBB11_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB11_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_sle:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvge a3, a1, a0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_sle:
; RV64: # %bb.0:
; RV64-NEXT: bge a1, a0, .LBB11_2
@@ -619,11 +723,11 @@ define i64 @select_i64_trunc(i64 %cond, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICM-LABEL: select_i64_trunc:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: mv a1, a3
+; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: andi a0, a0, 1
-; RV32-XQCICM-NEXT: qc.mveqi a2, a0, 0, a4
-; RV32-XQCICM-NEXT: qc.mveqi a1, a0, 0, a5
-; RV32-XQCICM-NEXT: mv a0, a2
+; RV32-XQCICM-NEXT: qc.mvnei a4, a0, 0, a2
+; RV32-XQCICM-NEXT: qc.mvnei a1, a0, 0, a3
+; RV32-XQCICM-NEXT: mv a0, a4
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_trunc:
@@ -634,6 +738,15 @@ define i64 @select_i64_trunc(i64 %cond, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a4
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_trunc:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: mv a1, a5
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.mvnei a4, a0, 0, a2
+; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a3
+; RV32IXQCI-NEXT: mv a0, a4
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_trunc:
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
@@ -679,10 +792,10 @@ define i64 @select_i64_param(i1 %cond, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-LABEL: select_i64_param:
; RV32-XQCICM: # %bb.0:
; RV32-XQCICM-NEXT: andi a0, a0, 1
-; RV32-XQCICM-NEXT: qc.mveqi a1, a0, 0, a3
-; RV32-XQCICM-NEXT: qc.mveqi a2, a0, 0, a4
-; RV32-XQCICM-NEXT: mv a0, a1
-; RV32-XQCICM-NEXT: mv a1, a2
+; RV32-XQCICM-NEXT: qc.mvnei a3, a0, 0, a1
+; RV32-XQCICM-NEXT: qc.mvnei a4, a0, 0, a2
+; RV32-XQCICM-NEXT: mv a0, a3
+; RV32-XQCICM-NEXT: mv a1, a4
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_param:
@@ -694,6 +807,15 @@ define i64 @select_i64_param(i1 %cond, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: mv a1, a5
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_param:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.mvnei a3, a0, 0, a1
+; RV32IXQCI-NEXT: qc.mvnei a4, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: mv a1, a4
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_param:
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
@@ -760,6 +882,17 @@ define i64 @select_i64_eq(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_eq:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: xor a1, a1, a3
+; RV32IXQCI-NEXT: xor a0, a0, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: qc.mveqi a6, a0, 0, a4
+; RV32IXQCI-NEXT: qc.mveqi a7, a0, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_eq:
; RV64: # %bb.0:
; RV64-NEXT: beq a0, a1, .LBB14_2
@@ -826,6 +959,17 @@ define i64 @select_i64_ne(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_ne:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: xor a1, a1, a3
+; RV32IXQCI-NEXT: xor a0, a0, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: qc.mvnei a6, a0, 0, a4
+; RV32IXQCI-NEXT: qc.mvnei a7, a0, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_ne:
; RV64: # %bb.0:
; RV64-NEXT: bne a0, a1, .LBB15_2
@@ -881,24 +1025,37 @@ define i64 @select_i64_ugt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a2, a0
; RV32-XQCICM-NEXT: sltu a2, a3, a1
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mveqi a4, a2, 0, a6
-; RV32-XQCICM-NEXT: qc.mveqi a5, a2, 0, a7
-; RV32-XQCICM-NEXT: mv a0, a4
-; RV32-XQCICM-NEXT: mv a1, a5
+; RV32-XQCICM-NEXT: qc.mvnei a6, a2, 0, a4
+; RV32-XQCICM-NEXT: qc.mvnei a7, a2, 0, a5
+; RV32-XQCICM-NEXT: mv a0, a6
+; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ugt:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: sltu t0, a3, a1
-; RV32-XQCICS-NEXT: sltu a0, a2, a0
-; RV32-XQCICS-NEXT: xor a1, a1, a3
-; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
+; RV32-XQCICS-NEXT: beq a1, a3, .LBB16_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: sltu a1, a3, a1
+; RV32-XQCICS-NEXT: j .LBB16_3
+; RV32-XQCICS-NEXT: .LBB16_2:
+; RV32-XQCICS-NEXT: sltu a1, a2, a0
+; RV32-XQCICS-NEXT: .LBB16_3:
; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_ugt:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a2, a0
+; RV32IXQCI-NEXT: sltu a2, a3, a1
+; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
+; RV32IXQCI-NEXT: qc.mvnei a6, a2, 0, a4
+; RV32IXQCI-NEXT: qc.mvnei a7, a2, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_ugt:
; RV64: # %bb.0:
; RV64-NEXT: bltu a1, a0, .LBB16_2
@@ -962,16 +1119,29 @@ define i64 @select_i64_uge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICS-LABEL: select_i64_uge:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: sltu t0, a1, a3
-; RV32-XQCICS-NEXT: sltu a0, a0, a2
-; RV32-XQCICS-NEXT: xor a1, a1, a3
-; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
+; RV32-XQCICS-NEXT: beq a1, a3, .LBB17_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: sltu a1, a1, a3
+; RV32-XQCICS-NEXT: j .LBB17_3
+; RV32-XQCICS-NEXT: .LBB17_2:
+; RV32-XQCICS-NEXT: sltu a1, a0, a2
+; RV32-XQCICS-NEXT: .LBB17_3:
; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a6, a4
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a7, a5
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_uge:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a0, a2
+; RV32IXQCI-NEXT: sltu a2, a1, a3
+; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
+; RV32IXQCI-NEXT: qc.mveqi a6, a2, 0, a4
+; RV32IXQCI-NEXT: qc.mveqi a7, a2, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_uge:
; RV64: # %bb.0:
; RV64-NEXT: bgeu a0, a1, .LBB17_2
@@ -1027,24 +1197,37 @@ define i64 @select_i64_ult(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a0, a2
; RV32-XQCICM-NEXT: sltu a2, a1, a3
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mveqi a4, a2, 0, a6
-; RV32-XQCICM-NEXT: qc.mveqi a5, a2, 0, a7
-; RV32-XQCICM-NEXT: mv a0, a4
-; RV32-XQCICM-NEXT: mv a1, a5
+; RV32-XQCICM-NEXT: qc.mvnei a6, a2, 0, a4
+; RV32-XQCICM-NEXT: qc.mvnei a7, a2, 0, a5
+; RV32-XQCICM-NEXT: mv a0, a6
+; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ult:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: sltu t0, a1, a3
-; RV32-XQCICS-NEXT: sltu a0, a0, a2
-; RV32-XQCICS-NEXT: xor a1, a1, a3
-; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
+; RV32-XQCICS-NEXT: beq a1, a3, .LBB18_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: sltu a1, a1, a3
+; RV32-XQCICS-NEXT: j .LBB18_3
+; RV32-XQCICS-NEXT: .LBB18_2:
+; RV32-XQCICS-NEXT: sltu a1, a0, a2
+; RV32-XQCICS-NEXT: .LBB18_3:
; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_ult:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a0, a2
+; RV32IXQCI-NEXT: sltu a2, a1, a3
+; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
+; RV32IXQCI-NEXT: qc.mvnei a6, a2, 0, a4
+; RV32IXQCI-NEXT: qc.mvnei a7, a2, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_ult:
; RV64: # %bb.0:
; RV64-NEXT: bltu a0, a1, .LBB18_2
@@ -1108,16 +1291,29 @@ define i64 @select_i64_ule(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICS-LABEL: select_i64_ule:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: sltu t0, a3, a1
-; RV32-XQCICS-NEXT: sltu a0, a2, a0
-; RV32-XQCICS-NEXT: xor a1, a1, a3
-; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
+; RV32-XQCICS-NEXT: beq a1, a3, .LBB19_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: sltu a1, a3, a1
+; RV32-XQCICS-NEXT: j .LBB19_3
+; RV32-XQCICS-NEXT: .LBB19_2:
+; RV32-XQCICS-NEXT: sltu a1, a2, a0
+; RV32-XQCICS-NEXT: .LBB19_3:
; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a6, a4
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a7, a5
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_ule:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a2, a0
+; RV32IXQCI-NEXT: sltu a2, a3, a1
+; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
+; RV32IXQCI-NEXT: qc.mveqi a6, a2, 0, a4
+; RV32IXQCI-NEXT: qc.mveqi a7, a2, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_ule:
; RV64: # %bb.0:
; RV64-NEXT: bgeu a1, a0, .LBB19_2
@@ -1173,24 +1369,37 @@ define i64 @select_i64_sgt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a2, a0
; RV32-XQCICM-NEXT: slt a2, a3, a1
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mveqi a4, a2, 0, a6
-; RV32-XQCICM-NEXT: qc.mveqi a5, a2, 0, a7
-; RV32-XQCICM-NEXT: mv a0, a4
-; RV32-XQCICM-NEXT: mv a1, a5
+; RV32-XQCICM-NEXT: qc.mvnei a6, a2, 0, a4
+; RV32-XQCICM-NEXT: qc.mvnei a7, a2, 0, a5
+; RV32-XQCICM-NEXT: mv a0, a6
+; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_sgt:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: slt t0, a3, a1
-; RV32-XQCICS-NEXT: sltu a0, a2, a0
-; RV32-XQCICS-NEXT: xor a1, a1, a3
-; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
+; RV32-XQCICS-NEXT: beq a1, a3, .LBB20_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: slt a1, a3, a1
+; RV32-XQCICS-NEXT: j .LBB20_3
+; RV32-XQCICS-NEXT: .LBB20_2:
+; RV32-XQCICS-NEXT: sltu a1, a2, a0
+; RV32-XQCICS-NEXT: .LBB20_3:
; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_sgt:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a2, a0
+; RV32IXQCI-NEXT: slt a2, a3, a1
+; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
+; RV32IXQCI-NEXT: qc.mvnei a6, a2, 0, a4
+; RV32IXQCI-NEXT: qc.mvnei a7, a2, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_sgt:
; RV64: # %bb.0:
; RV64-NEXT: blt a1, a0, .LBB20_2
@@ -1254,16 +1463,29 @@ define i64 @select_i64_sge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICS-LABEL: select_i64_sge:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: slt t0, a1, a3
-; RV32-XQCICS-NEXT: sltu a0, a0, a2
-; RV32-XQCICS-NEXT: xor a1, a1, a3
-; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
+; RV32-XQCICS-NEXT: beq a1, a3, .LBB21_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: slt a1, a1, a3
+; RV32-XQCICS-NEXT: j .LBB21_3
+; RV32-XQCICS-NEXT: .LBB21_2:
+; RV32-XQCICS-NEXT: sltu a1, a0, a2
+; RV32-XQCICS-NEXT: .LBB21_3:
; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a6, a4
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a7, a5
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_sge:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a0, a2
+; RV32IXQCI-NEXT: slt a2, a1, a3
+; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
+; RV32IXQCI-NEXT: qc.mveqi a6, a2, 0, a4
+; RV32IXQCI-NEXT: qc.mveqi a7, a2, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_sge:
; RV64: # %bb.0:
; RV64-NEXT: bge a0, a1, .LBB21_2
@@ -1319,24 +1541,37 @@ define i64 @select_i64_slt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a0, a2
; RV32-XQCICM-NEXT: slt a2, a1, a3
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mveqi a4, a2, 0, a6
-; RV32-XQCICM-NEXT: qc.mveqi a5, a2, 0, a7
-; RV32-XQCICM-NEXT: mv a0, a4
-; RV32-XQCICM-NEXT: mv a1, a5
+; RV32-XQCICM-NEXT: qc.mvnei a6, a2, 0, a4
+; RV32-XQCICM-NEXT: qc.mvnei a7, a2, 0, a5
+; RV32-XQCICM-NEXT: mv a0, a6
+; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_slt:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: slt t0, a1, a3
-; RV32-XQCICS-NEXT: sltu a0, a0, a2
-; RV32-XQCICS-NEXT: xor a1, a1, a3
-; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
+; RV32-XQCICS-NEXT: beq a1, a3, .LBB22_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: slt a1, a1, a3
+; RV32-XQCICS-NEXT: j .LBB22_3
+; RV32-XQCICS-NEXT: .LBB22_2:
+; RV32-XQCICS-NEXT: sltu a1, a0, a2
+; RV32-XQCICS-NEXT: .LBB22_3:
; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_slt:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a0, a2
+; RV32IXQCI-NEXT: slt a2, a1, a3
+; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
+; RV32IXQCI-NEXT: qc.mvnei a6, a2, 0, a4
+; RV32IXQCI-NEXT: qc.mvnei a7, a2, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_slt:
; RV64: # %bb.0:
; RV64-NEXT: blt a0, a1, .LBB22_2
@@ -1400,16 +1635,29 @@ define i64 @select_i64_sle(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICS-LABEL: select_i64_sle:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: slt t0, a3, a1
-; RV32-XQCICS-NEXT: sltu a0, a2, a0
-; RV32-XQCICS-NEXT: xor a1, a1, a3
-; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
+; RV32-XQCICS-NEXT: beq a1, a3, .LBB23_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: slt a1, a3, a1
+; RV32-XQCICS-NEXT: j .LBB23_3
+; RV32-XQCICS-NEXT: .LBB23_2:
+; RV32-XQCICS-NEXT: sltu a1, a2, a0
+; RV32-XQCICS-NEXT: .LBB23_3:
; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a6, a4
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a7, a5
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_sle:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a2, a0
+; RV32IXQCI-NEXT: slt a2, a3, a1
+; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
+; RV32IXQCI-NEXT: qc.mveqi a6, a2, 0, a4
+; RV32IXQCI-NEXT: qc.mveqi a7, a2, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_sle:
; RV64: # %bb.0:
; RV64-NEXT: bge a1, a0, .LBB23_2
diff --git a/llvm/test/CodeGen/RISCV/select-const.ll b/llvm/test/CodeGen/RISCV/select-const.ll
index 652018d023b86..65d10bb823418 100644
--- a/llvm/test/CodeGen/RISCV/select-const.ll
+++ b/llvm/test/CodeGen/RISCV/select-const.ll
@@ -5,6 +5,8 @@
; RUN: | FileCheck -check-prefixes=RV32,RV32IF %s
; RUN: llc -mtriple=riscv32 -mattr=+zicond -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32,RV32ZICOND %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64,RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi=lp64 -verify-machineinstrs < %s \
@@ -25,6 +27,10 @@ define signext i32 @select_const_int_easy(i1 zeroext %a) nounwind {
; RV32: # %bb.0:
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_const_int_easy:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_const_int_easy:
; RV64: # %bb.0:
; RV64-NEXT: ret
@@ -39,6 +45,12 @@ define signext i32 @select_const_int_one_away(i1 zeroext %a) nounwind {
; RV32-NEXT: sub a0, a1, a0
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_const_int_one_away:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 4
+; RV32IXQCI-NEXT: sub a0, a1, a0
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_const_int_one_away:
; RV64: # %bb.0:
; RV64-NEXT: li a1, 4
@@ -54,6 +66,11 @@ define signext i32 @select_const_int_pow2_zero(i1 zeroext %a) nounwind {
; RV32-NEXT: slli a0, a0, 2
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_const_int_pow2_zero:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: slli a0, a0, 2
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_const_int_pow2_zero:
; RV64: # %bb.0:
; RV64-NEXT: slli a0, a0, 2
@@ -90,6 +107,12 @@ define signext i32 @select_const_int_harder(i1 zeroext %a) nounwind {
; RV32ZICOND-NEXT: addi a0, a0, 6
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: select_const_int_harder:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 38
+; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a1, 6
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: select_const_int_harder:
; RV64I: # %bb.0:
; RV64I-NEXT: bnez a0, .LBB3_2
@@ -152,6 +175,14 @@ define float @select_const_fp(i1 zeroext %a) nounwind {
; RV32ZICOND-NEXT: add a0, a0, a1
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: select_const_fp:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: lui a2, 263168
+; RV32IXQCI-NEXT: lui a1, 264192
+; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: select_const_fp:
; RV64I: # %bb.0:
; RV64I-NEXT: mv a1, a0
@@ -194,6 +225,13 @@ define signext i32 @select_eq_zero_negone(i32 signext %a, i32 signext %b) nounwi
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_eq_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: snez a0, a0
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_eq_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
@@ -213,6 +251,13 @@ define signext i32 @select_ne_zero_negone(i32 signext %a, i32 signext %b) nounwi
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_ne_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: seqz a0, a0
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_ne_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
@@ -231,6 +276,12 @@ define signext i32 @select_sgt_zero_negone(i32 signext %a, i32 signext %b) nounw
; RV32-NEXT: neg a0, a0
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_sgt_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: slt a0, a1, a0
+; RV32IXQCI-NEXT: neg a0, a0
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_sgt_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: slt a0, a1, a0
@@ -248,6 +299,12 @@ define signext i32 @select_slt_zero_negone(i32 signext %a, i32 signext %b) nounw
; RV32-NEXT: neg a0, a0
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_slt_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: slt a0, a0, a1
+; RV32IXQCI-NEXT: neg a0, a0
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_slt_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: slt a0, a0, a1
@@ -265,6 +322,12 @@ define signext i32 @select_sge_zero_negone(i32 signext %a, i32 signext %b) nounw
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_sge_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: slt a0, a0, a1
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_sge_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: slt a0, a0, a1
@@ -282,6 +345,12 @@ define signext i32 @select_sle_zero_negone(i32 signext %a, i32 signext %b) nounw
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_sle_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: slt a0, a1, a0
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_sle_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: slt a0, a1, a0
@@ -299,6 +368,12 @@ define signext i32 @select_ugt_zero_negone(i32 signext %a, i32 signext %b) nounw
; RV32-NEXT: neg a0, a0
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_ugt_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a1, a0
+; RV32IXQCI-NEXT: neg a0, a0
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_ugt_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: sltu a0, a1, a0
@@ -316,6 +391,12 @@ define signext i32 @select_ult_zero_negone(i32 signext %a, i32 signext %b) nounw
; RV32-NEXT: neg a0, a0
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_ult_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a0, a1
+; RV32IXQCI-NEXT: neg a0, a0
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_ult_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: sltu a0, a0, a1
@@ -333,6 +414,12 @@ define signext i32 @select_uge_zero_negone(i32 signext %a, i32 signext %b) nounw
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_uge_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a0, a1
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_uge_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: sltu a0, a0, a1
@@ -350,6 +437,12 @@ define signext i32 @select_ule_zero_negone(i32 signext %a, i32 signext %b) nounw
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_ule_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a1, a0
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_ule_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: sltu a0, a1, a0
@@ -368,6 +461,13 @@ define i32 @select_eq_1_2(i32 signext %a, i32 signext %b) {
; RV32-NEXT: addi a0, a0, 1
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_eq_1_2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: snez a0, a0
+; RV32IXQCI-NEXT: addi a0, a0, 1
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_eq_1_2:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
@@ -387,6 +487,13 @@ define i32 @select_ne_1_2(i32 signext %a, i32 signext %b) {
; RV32-NEXT: addi a0, a0, 1
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_ne_1_2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: seqz a0, a0
+; RV32IXQCI-NEXT: addi a0, a0, 1
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_ne_1_2:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
@@ -408,6 +515,15 @@ define i32 @select_eq_10000_10001(i32 signext %a, i32 signext %b) {
; RV32-NEXT: sub a0, a1, a0
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_eq_10000_10001:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: lui a1, 2
+; RV32IXQCI-NEXT: seqz a0, a0
+; RV32IXQCI-NEXT: addi a1, a1, 1810
+; RV32IXQCI-NEXT: sub a0, a1, a0
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_eq_10000_10001:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
@@ -431,6 +547,15 @@ define i32 @select_ne_10001_10002(i32 signext %a, i32 signext %b) {
; RV32-NEXT: sub a0, a1, a0
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_ne_10001_10002:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: lui a1, 2
+; RV32IXQCI-NEXT: snez a0, a0
+; RV32IXQCI-NEXT: addi a1, a1, 1810
+; RV32IXQCI-NEXT: sub a0, a1, a0
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_ne_10001_10002:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
@@ -452,6 +577,13 @@ define i32 @select_slt_zero_constant1_constant2(i32 signext %x) {
; RV32-NEXT: addi a0, a0, -3
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_slt_zero_constant1_constant2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: srai a0, a0, 31
+; RV32IXQCI-NEXT: andi a0, a0, 10
+; RV32IXQCI-NEXT: addi a0, a0, -3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_slt_zero_constant1_constant2:
; RV64: # %bb.0:
; RV64-NEXT: srai a0, a0, 63
@@ -471,6 +603,13 @@ define i32 @select_sgt_negative_one_constant1_constant2(i32 signext %x) {
; RV32-NEXT: addi a0, a0, 7
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_sgt_negative_one_constant1_constant2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: srai a0, a0, 31
+; RV32IXQCI-NEXT: andi a0, a0, -10
+; RV32IXQCI-NEXT: addi a0, a0, 7
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_sgt_negative_one_constant1_constant2:
; RV64: # %bb.0:
; RV64-NEXT: srai a0, a0, 63
@@ -512,6 +651,16 @@ define i32 @select_nonnegative_lui_addi(i32 signext %x) {
; RV32ZICOND-NEXT: addi a0, a0, 25
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: select_nonnegative_lui_addi:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: mv a1, a0
+; RV32IXQCI-NEXT: lui a0, 4
+; RV32IXQCI-NEXT: bgez a1, .LBB21_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: li a0, 25
+; RV32IXQCI-NEXT: .LBB21_2:
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: select_nonnegative_lui_addi:
; RV64I: # %bb.0:
; RV64I-NEXT: mv a1, a0
@@ -575,6 +724,16 @@ define i32 @select_nonnegative_lui_addi_swapped(i32 signext %x) {
; RV32ZICOND-NEXT: addi a0, a0, 25
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: select_nonnegative_lui_addi_swapped:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: bgez a0, .LBB22_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: lui a0, 4
+; RV32IXQCI-NEXT: ret
+; RV32IXQCI-NEXT: .LBB22_2:
+; RV32IXQCI-NEXT: li a0, 25
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: select_nonnegative_lui_addi_swapped:
; RV64I: # %bb.0:
; RV64I-NEXT: bgez a0, .LBB22_2
@@ -640,6 +799,17 @@ define i32 @
diff _shl_addi(i32 signext %x) {
; RV32ZICOND-NEXT: addi a0, a0, 25
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL:
diff _shl_addi:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: bgez a0, .LBB23_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: lui a0, 4
+; RV32IXQCI-NEXT: addi a0, a0, 25
+; RV32IXQCI-NEXT: ret
+; RV32IXQCI-NEXT: .LBB23_2:
+; RV32IXQCI-NEXT: li a0, 25
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL:
diff _shl_addi:
; RV64I: # %bb.0:
; RV64I-NEXT: bgez a0, .LBB23_2
@@ -704,6 +874,17 @@ define i32 @
diff _shl_addi2(i32 signext %x) {
; RV32ZICOND-NEXT: addi a0, a0, 25
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL:
diff _shl_addi2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: bgez a0, .LBB24_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: li a0, 25
+; RV32IXQCI-NEXT: ret
+; RV32IXQCI-NEXT: .LBB24_2:
+; RV32IXQCI-NEXT: lui a0, 4
+; RV32IXQCI-NEXT: addi a0, a0, 25
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL:
diff _shl_addi2:
; RV64I: # %bb.0:
; RV64I-NEXT: bgez a0, .LBB24_2
@@ -746,6 +927,13 @@ define i32 @
diff _pow2_24_16(i32 signext %x) {
; RV32-NEXT: addi a0, a0, 24
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL:
diff _pow2_24_16:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: srai a0, a0, 31
+; RV32IXQCI-NEXT: andi a0, a0, -8
+; RV32IXQCI-NEXT: addi a0, a0, 24
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL:
diff _pow2_24_16:
; RV64: # %bb.0:
; RV64-NEXT: srai a0, a0, 63
@@ -765,6 +953,13 @@ define i32 @
diff _pow2_16_24(i32 signext %x) {
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL:
diff _pow2_16_24:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: srli a0, a0, 28
+; RV32IXQCI-NEXT: andi a0, a0, 8
+; RV32IXQCI-NEXT: addi a0, a0, 16
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL:
diff _pow2_16_24:
; RV64: # %bb.0:
; RV64-NEXT: srli a0, a0, 60
@@ -811,6 +1006,18 @@ define i32 @zext_or_constant(i32 signext %x) {
; RV32ZICOND-NEXT: or a0, a2, a0
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: zext_or_constant:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: bgez a0, .LBB27_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: lui a0, 140
+; RV32IXQCI-NEXT: addi a0, a0, 417
+; RV32IXQCI-NEXT: ret
+; RV32IXQCI-NEXT: .LBB27_2:
+; RV32IXQCI-NEXT: srli a0, a0, 31
+; RV32IXQCI-NEXT: xori a0, a0, 1
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: zext_or_constant:
; RV64I: # %bb.0:
; RV64I-NEXT: bgez a0, .LBB27_2
@@ -886,6 +1093,18 @@ define i32 @zext_or_constant2(i32 signext %x) {
; RV32ZICOND-NEXT: or a0, a1, a0
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: zext_or_constant2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: bltz a0, .LBB28_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: lui a0, 140
+; RV32IXQCI-NEXT: addi a0, a0, 417
+; RV32IXQCI-NEXT: ret
+; RV32IXQCI-NEXT: .LBB28_2:
+; RV32IXQCI-NEXT: srli a0, a0, 31
+; RV32IXQCI-NEXT: xori a0, a0, 1
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: zext_or_constant2:
; RV64I: # %bb.0:
; RV64I-NEXT: bltz a0, .LBB28_2
@@ -962,6 +1181,18 @@ define i32 @sext_or_constant(i32 signext %x) {
; RV32ZICOND-NEXT: or a0, a0, a1
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: sext_or_constant:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: bgez a0, .LBB29_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: lui a0, 140
+; RV32IXQCI-NEXT: addi a0, a0, 417
+; RV32IXQCI-NEXT: ret
+; RV32IXQCI-NEXT: .LBB29_2:
+; RV32IXQCI-NEXT: srli a0, a0, 31
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: sext_or_constant:
; RV64I: # %bb.0:
; RV64I-NEXT: bgez a0, .LBB29_2
@@ -1038,6 +1269,18 @@ define i32 @sext_or_constant2(i32 signext %x) {
; RV32ZICOND-NEXT: or a0, a1, a0
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: sext_or_constant2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: bltz a0, .LBB30_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: lui a0, 140
+; RV32IXQCI-NEXT: addi a0, a0, 417
+; RV32IXQCI-NEXT: ret
+; RV32IXQCI-NEXT: .LBB30_2:
+; RV32IXQCI-NEXT: srli a0, a0, 31
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: sext_or_constant2:
; RV64I: # %bb.0:
; RV64I-NEXT: bltz a0, .LBB30_2
@@ -1087,6 +1330,13 @@ define i32 @select_0_6(i32 signext %x) {
; RV32-NEXT: slli a0, a0, 1
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_0_6:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: srai a0, a0, 2
+; RV32IXQCI-NEXT: srli a0, a0, 30
+; RV32IXQCI-NEXT: slli a0, a0, 1
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_0_6:
; RV64: # %bb.0:
; RV64-NEXT: srai a0, a0, 2
@@ -1106,6 +1356,13 @@ define i32 @select_6_0(i32 signext %x) {
; RV32-NEXT: andi a0, a0, 6
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_6_0:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: srli a0, a0, 31
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: andi a0, a0, 6
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_6_0:
; RV64: # %bb.0:
; RV64-NEXT: srli a0, a0, 63
@@ -1124,6 +1381,12 @@ define i32 @select_0_394(i32 signext %x) {
; RV32-NEXT: andi a0, a0, 394
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_0_394:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: srai a0, a0, 31
+; RV32IXQCI-NEXT: andi a0, a0, 394
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_0_394:
; RV64: # %bb.0:
; RV64-NEXT: srai a0, a0, 63
@@ -1142,6 +1405,13 @@ define i32 @select_394_0(i32 signext %x) {
; RV32-NEXT: andi a0, a0, 394
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_394_0:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: srli a0, a0, 31
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: andi a0, a0, 394
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_394_0:
; RV64: # %bb.0:
; RV64-NEXT: srli a0, a0, 63
diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll
index b5a76911dda13..19fade67afc3d 100644
--- a/llvm/test/CodeGen/RISCV/select.ll
+++ b/llvm/test/CodeGen/RISCV/select.ll
@@ -4,6 +4,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+m,+xventanacondops -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64IMXVTCONDOPS %s
; RUN: llc -mtriple=riscv32 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV32IMZICOND %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV64IMZICOND %s
+; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
define i16 @select_xor_1(i16 %A, i8 %cond) {
; RV32IM-LABEL: select_xor_1:
@@ -39,6 +41,14 @@ define i16 @select_xor_1(i16 %A, i8 %cond) {
; CHECKZICOND-NEXT: andi a1, a1, 43
; CHECKZICOND-NEXT: xor a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_xor_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: slli a1, a1, 31
+; RV32IXQCI-NEXT: srai a1, a1, 31
+; RV32IXQCI-NEXT: andi a1, a1, 43
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp eq i8 %and, 0
@@ -89,6 +99,14 @@ define i16 @select_xor_1b(i16 %A, i8 %cond) {
; RV64IMZICOND-NEXT: andi a1, a1, 43
; RV64IMZICOND-NEXT: xor a0, a0, a1
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_xor_1b:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: slli a1, a1, 31
+; RV32IXQCI-NEXT: srai a1, a1, 31
+; RV32IXQCI-NEXT: andi a1, a1, 43
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp ne i8 %and, 1
@@ -127,6 +145,14 @@ define i32 @select_xor_2(i32 %A, i32 %B, i8 %cond) {
; CHECKZICOND-NEXT: czero.eqz a1, a1, a2
; CHECKZICOND-NEXT: xor a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_xor_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: slli a2, a2, 31
+; RV32IXQCI-NEXT: srai a2, a2, 31
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp eq i8 %and, 0
@@ -167,6 +193,14 @@ define i32 @select_xor_2b(i32 %A, i32 %B, i8 %cond) {
; CHECKZICOND-NEXT: czero.eqz a1, a1, a2
; CHECKZICOND-NEXT: xor a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_xor_2b:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: slli a2, a2, 31
+; RV32IXQCI-NEXT: srai a2, a2, 31
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp ne i8 %and, 1
@@ -183,6 +217,14 @@ define i16 @select_xor_3(i16 %A, i8 %cond) {
; CHECK-NEXT: andi a1, a1, 43
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_xor_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a1, a1, 1
+; RV32IXQCI-NEXT: addi a1, a1, -1
+; RV32IXQCI-NEXT: andi a1, a1, 43
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp eq i8 %and, 0
@@ -201,6 +243,14 @@ define i16 @select_xor_3b(i16 %A, i8 %cond) {
; CHECK-NEXT: andi a1, a1, 43
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_xor_3b:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a1, a1, 1
+; RV32IXQCI-NEXT: addi a1, a1, -1
+; RV32IXQCI-NEXT: andi a1, a1, 43
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp ne i8 %and, 1
@@ -239,6 +289,14 @@ define i32 @select_xor_4(i32 %A, i32 %B, i8 %cond) {
; CHECKZICOND-NEXT: czero.nez a1, a1, a2
; CHECKZICOND-NEXT: xor a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_xor_4:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: addi a2, a2, -1
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp eq i8 %and, 0
@@ -279,6 +337,14 @@ define i32 @select_xor_4b(i32 %A, i32 %B, i8 %cond) {
; CHECKZICOND-NEXT: czero.nez a1, a1, a2
; CHECKZICOND-NEXT: xor a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_xor_4b:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: addi a2, a2, -1
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp ne i8 %and, 1
@@ -313,6 +379,13 @@ define i32 @select_xor_5(i1 zeroext %cond, i32 %x) {
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
; CHECKZICOND-NEXT: xori a0, a0, 128
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_xor_5:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: and a0, a0, a1
+; RV32IXQCI-NEXT: xori a0, a0, 128
+; RV32IXQCI-NEXT: ret
%add = xor i32 %x, 128
%sel = select i1 %cond, i32 128, i32 %add
ret i32 %sel
@@ -348,6 +421,14 @@ define i32 @select_or(i32 %A, i32 %B, i8 %cond) {
; CHECKZICOND-NEXT: czero.eqz a1, a1, a2
; CHECKZICOND-NEXT: or a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_or:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: slli a2, a2, 31
+; RV32IXQCI-NEXT: srai a2, a2, 31
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp eq i8 %and, 0
@@ -388,6 +469,14 @@ define i32 @select_or_b(i32 %A, i32 %B, i8 %cond) {
; CHECKZICOND-NEXT: czero.eqz a1, a1, a2
; CHECKZICOND-NEXT: or a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_or_b:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: slli a2, a2, 31
+; RV32IXQCI-NEXT: srai a2, a2, 31
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp ne i8 %and, 1
@@ -426,6 +515,14 @@ define i32 @select_or_1(i32 %A, i32 %B, i32 %cond) {
; CHECKZICOND-NEXT: czero.eqz a1, a1, a2
; CHECKZICOND-NEXT: or a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_or_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: slli a2, a2, 31
+; RV32IXQCI-NEXT: srai a2, a2, 31
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i32 %cond, 1
%cmp10 = icmp eq i32 %and, 0
@@ -466,6 +563,14 @@ define i32 @select_or_1b(i32 %A, i32 %B, i32 %cond) {
; CHECKZICOND-NEXT: czero.eqz a1, a1, a2
; CHECKZICOND-NEXT: or a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_or_1b:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: slli a2, a2, 31
+; RV32IXQCI-NEXT: srai a2, a2, 31
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i32 %cond, 1
%cmp10 = icmp ne i32 %and, 1
@@ -504,6 +609,14 @@ define i32 @select_or_2(i32 %A, i32 %B, i8 %cond) {
; CHECKZICOND-NEXT: czero.nez a1, a1, a2
; CHECKZICOND-NEXT: or a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_or_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: addi a2, a2, -1
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp eq i8 %and, 0
@@ -544,6 +657,14 @@ define i32 @select_or_2b(i32 %A, i32 %B, i8 %cond) {
; CHECKZICOND-NEXT: czero.nez a1, a1, a2
; CHECKZICOND-NEXT: or a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_or_2b:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: addi a2, a2, -1
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp ne i8 %and, 1
@@ -582,6 +703,14 @@ define i32 @select_or_3(i32 %A, i32 %B, i32 %cond) {
; CHECKZICOND-NEXT: czero.nez a1, a1, a2
; CHECKZICOND-NEXT: or a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_or_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: addi a2, a2, -1
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i32 %cond, 1
%cmp10 = icmp eq i32 %and, 0
@@ -622,6 +751,14 @@ define i32 @select_or_3b(i32 %A, i32 %B, i32 %cond) {
; CHECKZICOND-NEXT: czero.nez a1, a1, a2
; CHECKZICOND-NEXT: or a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_or_3b:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: addi a2, a2, -1
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i32 %cond, 1
%cmp10 = icmp ne i32 %and, 1
@@ -656,6 +793,13 @@ define i32 @select_or_4(i1 zeroext %cond, i32 %x) {
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
; CHECKZICOND-NEXT: ori a0, a0, 128
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_or_4:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: and a0, a0, a1
+; RV32IXQCI-NEXT: ori a0, a0, 128
+; RV32IXQCI-NEXT: ret
%add = or i32 %x, 128
%sel = select i1 %cond, i32 128, i32 %add
ret i32 %sel
@@ -693,6 +837,13 @@ define i32 @select_add_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0
; RV64IMZICOND-NEXT: addw a0, a2, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_add_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: neg a0, a0
+; RV32IXQCI-NEXT: and a0, a0, a1
+; RV32IXQCI-NEXT: add a0, a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = add i32 %a, %b
%res = select i1 %cond, i32 %c, i32 %b
@@ -731,6 +882,13 @@ define i32 @select_add_2(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: addw a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_add_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: and a0, a0, a2
+; RV32IXQCI-NEXT: add a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%c = add i32 %a, %b
%res = select i1 %cond, i32 %a, i32 %c
@@ -772,6 +930,13 @@ define i32 @select_add_3(i1 zeroext %cond, i32 %a) {
; RV64IMZICOND-NEXT: andi a0, a0, 42
; RV64IMZICOND-NEXT: addw a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_add_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: andi a0, a0, 42
+; RV32IXQCI-NEXT: add a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%c = add i32 %a, 42
%res = select i1 %cond, i32 %a, i32 %c
@@ -810,6 +975,13 @@ define i32 @select_add_4(i1 zeroext %cond, i32 %x) {
; RV64IMZICOND-NEXT: czero.nez a0, a1, a0
; RV64IMZICOND-NEXT: addiw a0, a0, 128
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_add_4:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: and a0, a0, a1
+; RV32IXQCI-NEXT: addi a0, a0, 128
+; RV32IXQCI-NEXT: ret
%add = add i32 %x, 128
%sel = select i1 %cond, i32 128, i32 %add
ret i32 %sel
@@ -854,6 +1026,16 @@ define i64 @select_add_5(i1 zeroext %cond, i64 %x) {
; RV64IMZICOND-NEXT: czero.nez a0, a1, a0
; RV64IMZICOND-NEXT: addi a0, a0, 128
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_add_5:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: addi a3, a0, -1
+; RV32IXQCI-NEXT: and a1, a1, a3
+; RV32IXQCI-NEXT: addi a0, a1, 128
+; RV32IXQCI-NEXT: sltu a1, a0, a1
+; RV32IXQCI-NEXT: and a2, a2, a3
+; RV32IXQCI-NEXT: add a1, a1, a2
+; RV32IXQCI-NEXT: ret
%add = add i64 %x, 128
%sel = select i1 %cond, i64 128, i64 %add
ret i64 %sel
@@ -908,6 +1090,18 @@ define i64 @select_add_6(i1 zeroext %cond, i64 %x) {
; RV64IMZICOND-NEXT: addi a1, a1, 1005
; RV64IMZICOND-NEXT: add a0, a0, a1
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_add_6:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: addi a3, a0, -1
+; RV32IXQCI-NEXT: lui a0, 14
+; RV32IXQCI-NEXT: and a1, a1, a3
+; RV32IXQCI-NEXT: addi a0, a0, 1005
+; RV32IXQCI-NEXT: add a0, a0, a1
+; RV32IXQCI-NEXT: sltu a1, a0, a1
+; RV32IXQCI-NEXT: and a2, a2, a3
+; RV32IXQCI-NEXT: add a1, a1, a2
+; RV32IXQCI-NEXT: ret
%add = add i64 %x, 58349
%sel = select i1 %cond, i64 58349, i64 %add
ret i64 %sel
@@ -955,6 +1149,13 @@ define i32 @select_sub_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0
; RV64IMZICOND-NEXT: or a0, a0, a2
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_sub_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: sub a1, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = sub i32 %a, %b
%res = select i1 %cond, i32 %c, i32 %b
@@ -993,6 +1194,13 @@ define i32 @select_sub_2(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: subw a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_sub_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: and a0, a0, a2
+; RV32IXQCI-NEXT: sub a0, a1, a0
+; RV32IXQCI-NEXT: ret
entry:
%c = sub i32 %a, %b
%res = select i1 %cond, i32 %a, i32 %c
@@ -1034,6 +1242,13 @@ define i32 @select_sub_3(i1 zeroext %cond, i32 %a) {
; RV64IMZICOND-NEXT: andi a0, a0, 42
; RV64IMZICOND-NEXT: subw a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_sub_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: andi a0, a0, 42
+; RV32IXQCI-NEXT: sub a0, a1, a0
+; RV32IXQCI-NEXT: ret
entry:
%c = sub i32 %a, 42
%res = select i1 %cond, i32 %a, i32 %c
@@ -1083,6 +1298,14 @@ define i32 @select_sub_4(i1 zeroext %cond, i32 %x) {
; RV64IMZICOND-NEXT: czero.nez a0, a1, a0
; RV64IMZICOND-NEXT: addi a0, a0, 128
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_sub_4:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: addi a1, a1, -128
+; RV32IXQCI-NEXT: li a2, 128
+; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: ret
%add = sub i32 %x, 128
%sel = select i1 %cond, i32 128, i32 %add
ret i32 %sel
@@ -1121,6 +1344,13 @@ define i32 @select_and_1(i1 zeroext %cond, i32 %a, i32 %b) {
; CHECKZICOND-NEXT: czero.nez a0, a2, a0
; CHECKZICOND-NEXT: or a0, a1, a0
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_and_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = and i32 %a, %b
%res = select i1 %cond, i32 %c, i32 %b
@@ -1159,6 +1389,13 @@ define i32 @select_and_2(i1 zeroext %cond, i32 %a, i32 %b) {
; CHECKZICOND-NEXT: czero.eqz a0, a1, a0
; CHECKZICOND-NEXT: or a0, a2, a0
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_and_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: and a2, a2, a1
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = and i32 %a, %b
%res = select i1 %cond, i32 %a, i32 %c
@@ -1197,6 +1434,13 @@ define i32 @select_and_3(i1 zeroext %cond, i32 %a) {
; CHECKZICOND-NEXT: czero.eqz a0, a1, a0
; CHECKZICOND-NEXT: or a0, a2, a0
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_and_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a2, a1, 42
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = and i32 %a, 42
%res = select i1 %cond, i32 %a, i32 %c
@@ -1245,6 +1489,13 @@ define i32 @select_udiv_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0
; RV64IMZICOND-NEXT: or a0, a0, a2
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_udiv_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: divu a1, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = udiv i32 %a, %b
%res = select i1 %cond, i32 %c, i32 %b
@@ -1293,6 +1544,13 @@ define i32 @select_udiv_2(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: or a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_udiv_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: divu a2, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = udiv i32 %a, %b
%res = select i1 %cond, i32 %a, i32 %c
@@ -1361,6 +1619,17 @@ define i32 @select_udiv_3(i1 zeroext %cond, i32 %a) {
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: or a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_udiv_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: srli a2, a1, 1
+; RV32IXQCI-NEXT: lui a3, 199729
+; RV32IXQCI-NEXT: addi a3, a3, -975
+; RV32IXQCI-NEXT: mulhu a2, a2, a3
+; RV32IXQCI-NEXT: srli a2, a2, 2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = udiv i32 %a, 42
%res = select i1 %cond, i32 %a, i32 %c
@@ -1409,6 +1678,13 @@ define i32 @select_shl_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0
; RV64IMZICOND-NEXT: or a0, a0, a2
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_shl_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: sll a1, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = shl i32 %a, %b
%res = select i1 %cond, i32 %c, i32 %b
@@ -1447,6 +1723,13 @@ define i32 @select_shl_2(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: sllw a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_shl_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: and a0, a0, a2
+; RV32IXQCI-NEXT: sll a0, a1, a0
+; RV32IXQCI-NEXT: ret
entry:
%c = shl i32 %a, %b
%res = select i1 %cond, i32 %a, i32 %c
@@ -1458,6 +1741,11 @@ define i32 @select_shl_3(i1 zeroext %cond, i32 %a) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_shl_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%c = shl i32 %a, 42
%res = select i1 %cond, i32 %a, i32 %c
@@ -1506,6 +1794,13 @@ define i32 @select_ashr_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0
; RV64IMZICOND-NEXT: or a0, a0, a2
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_ashr_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: sra a1, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = ashr i32 %a, %b
%res = select i1 %cond, i32 %c, i32 %b
@@ -1544,6 +1839,13 @@ define i32 @select_ashr_2(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: sraw a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_ashr_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: and a0, a0, a2
+; RV32IXQCI-NEXT: sra a0, a1, a0
+; RV32IXQCI-NEXT: ret
entry:
%c = ashr i32 %a, %b
%res = select i1 %cond, i32 %a, i32 %c
@@ -1555,6 +1857,11 @@ define i32 @select_ashr_3(i1 zeroext %cond, i32 %a) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_ashr_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%c = ashr i32 %a, 42
%res = select i1 %cond, i32 %a, i32 %c
@@ -1603,6 +1910,13 @@ define i32 @select_lshr_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0
; RV64IMZICOND-NEXT: or a0, a0, a2
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_lshr_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: srl a1, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = lshr i32 %a, %b
%res = select i1 %cond, i32 %c, i32 %b
@@ -1641,6 +1955,13 @@ define i32 @select_lshr_2(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: srlw a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_lshr_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: and a0, a0, a2
+; RV32IXQCI-NEXT: srl a0, a1, a0
+; RV32IXQCI-NEXT: ret
entry:
%c = lshr i32 %a, %b
%res = select i1 %cond, i32 %a, i32 %c
@@ -1652,6 +1973,11 @@ define i32 @select_lshr_3(i1 zeroext %cond, i32 %a) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_lshr_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%c = lshr i32 %a, 42
%res = select i1 %cond, i32 %a, i32 %c
@@ -1665,6 +1991,13 @@ define i32 @select_cst_not1(i32 signext %a, i32 signext %b) {
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: xori a0, a0, -6
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_not1:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: slt a0, a0, a1
+; RV32IXQCI-NEXT: neg a0, a0
+; RV32IXQCI-NEXT: xori a0, a0, -6
+; RV32IXQCI-NEXT: ret
%cond = icmp slt i32 %a, %b
%ret = select i1 %cond, i32 5, i32 -6
ret i32 %ret
@@ -1676,6 +2009,12 @@ define i32 @select_cst_not2(i32 signext %a) {
; CHECK-NEXT: srai a0, a0, 31
; CHECK-NEXT: xori a0, a0, -6
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_not2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: srai a0, a0, 31
+; RV32IXQCI-NEXT: xori a0, a0, -6
+; RV32IXQCI-NEXT: ret
%cond = icmp slt i32 %a, 0
%ret = select i1 %cond, i32 5, i32 -6
ret i32 %ret
@@ -1687,6 +2026,12 @@ define i32 @select_cst_not3(i32 signext %a) {
; CHECK-NEXT: srai a0, a0, 31
; CHECK-NEXT: xori a0, a0, 5
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_not3:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: srai a0, a0, 31
+; RV32IXQCI-NEXT: xori a0, a0, 5
+; RV32IXQCI-NEXT: ret
%cond = icmp sgt i32 %a, -1
%ret = select i1 %cond, i32 5, i32 -6
ret i32 %ret
@@ -1735,6 +2080,14 @@ define i32 @select_cst_not4(i32 signext %a, i32 signext %b) {
; RV64IMZICOND-NEXT: addiw a1, a1, -1
; RV64IMZICOND-NEXT: xor a0, a0, a1
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_not4:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: slt a0, a0, a1
+; RV32IXQCI-NEXT: lui a1, 524288
+; RV32IXQCI-NEXT: addi a1, a1, -1
+; RV32IXQCI-NEXT: add a0, a0, a1
+; RV32IXQCI-NEXT: ret
%cond = icmp slt i32 %a, %b
%ret = select i1 %cond, i32 -2147483648, i32 2147483647
ret i32 %ret
@@ -1749,6 +2102,15 @@ define i32 @select_cst_not5(i32 signext %a, i32 signext %b) {
; CHECK-NEXT: addi a1, a1, -5
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_not5:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: slt a0, a0, a1
+; RV32IXQCI-NEXT: lui a1, 16
+; RV32IXQCI-NEXT: neg a0, a0
+; RV32IXQCI-NEXT: addi a1, a1, -5
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
%cond = icmp slt i32 %a, %b
%ret = select i1 %cond, i32 -65532, i32 65531
ret i32 %ret
@@ -1790,6 +2152,13 @@ define i32 @select_cst_unknown(i32 signext %a, i32 signext %b) {
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
; CHECKZICOND-NEXT: addi a0, a0, 5
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_unknown:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a2, -7
+; RV32IXQCI-NEXT: qc.lilt a2, a0, a1, 5
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
%cond = icmp slt i32 %a, %b
%ret = select i1 %cond, i32 5, i32 -7
ret i32 %ret
@@ -1829,6 +2198,12 @@ define i32 @select_cst1(i1 zeroext %cond) {
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
; CHECKZICOND-NEXT: addi a0, a0, 10
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst1:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 20
+; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a1, 10
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 10, i32 20
ret i32 %ret
}
@@ -1871,6 +2246,13 @@ define i32 @select_cst2(i1 zeroext %cond) {
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
; CHECKZICOND-NEXT: addi a0, a0, 10
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: lui a1, 5
+; RV32IXQCI-NEXT: addi a1, a1, -480
+; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a1, 10
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 10, i32 20000
ret i32 %ret
}
@@ -1919,6 +2301,16 @@ define i32 @select_cst3(i1 zeroext %cond) {
; CHECKZICOND-NEXT: addi a1, a1, 1328
; CHECKZICOND-NEXT: add a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst3:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: lui a1, 7
+; RV32IXQCI-NEXT: lui a2, 5
+; RV32IXQCI-NEXT: addi a3, a1, 1328
+; RV32IXQCI-NEXT: addi a1, a2, -480
+; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a3
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 30000, i32 20000
ret i32 %ret
}
@@ -1929,6 +2321,12 @@ define i32 @select_cst4(i1 zeroext %cond) {
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: xori a0, a0, 2047
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst4:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: neg a0, a0
+; RV32IXQCI-NEXT: xori a0, a0, 2047
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 -2048, i32 2047
ret i32 %ret
}
@@ -1969,6 +2367,15 @@ define i32 @select_cst5(i1 zeroext %cond) {
; CHECKZICOND-NEXT: slli a0, a0, 1
; CHECKZICOND-NEXT: addi a0, a0, 2047
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst5:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: lui a1, 1
+; RV32IXQCI-NEXT: addi a1, a1, -2047
+; RV32IXQCI-NEXT: li a2, 2047
+; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 2047, i32 2049
ret i32 %ret
}
@@ -2007,6 +2414,15 @@ define i32 @select_cst5_invert(i1 zeroext %cond) {
; CHECKZICOND-NEXT: slli a0, a0, 1
; CHECKZICOND-NEXT: addi a0, a0, 2047
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst5_invert:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: lui a1, 1
+; RV32IXQCI-NEXT: addi a2, a1, -2047
+; RV32IXQCI-NEXT: li a1, 2047
+; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 2049, i32 2047
ret i32 %ret
}
@@ -2052,6 +2468,14 @@ define i32 @select_cst_
diff 2(i1 zeroext %cond) {
; RV64IMZICOND-NEXT: slli a0, a0, 1
; RV64IMZICOND-NEXT: addiw a0, a0, 120
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_
diff 2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a2, 120
+; RV32IXQCI-NEXT: li a1, 122
+; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 120, i32 122
ret i32 %ret
}
@@ -2094,6 +2518,14 @@ define i32 @select_cst_
diff 2_invert(i1 zeroext %cond) {
; RV64IMZICOND-NEXT: slli a0, a0, 1
; RV64IMZICOND-NEXT: addiw a0, a0, 120
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_
diff 2_invert:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a2, 122
+; RV32IXQCI-NEXT: li a1, 120
+; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 122, i32 120
ret i32 %ret
}
@@ -2130,6 +2562,12 @@ define i32 @select_cst_
diff 4(i1 zeroext %cond) {
; CHECKZICOND-NEXT: slli a0, a0, 2
; CHECKZICOND-NEXT: addi a0, a0, 6
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_
diff 4:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 10
+; RV32IXQCI-NEXT: qc.selectinei a0, 0, a1, 6
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 10, i32 6
ret i32 %ret
}
@@ -2168,6 +2606,12 @@ define i32 @select_cst_
diff 4_invert(i1 zeroext %cond) {
; CHECKZICOND-NEXT: slli a0, a0, 2
; CHECKZICOND-NEXT: addi a0, a0, 6
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_
diff 4_invert:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 6
+; RV32IXQCI-NEXT: qc.selectinei a0, 0, a1, 10
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 6, i32 10
ret i32 %ret
}
@@ -2210,6 +2654,12 @@ define i32 @select_cst_
diff 8(i1 zeroext %cond) {
; RV64IMZICOND-NEXT: slli a0, a0, 3
; RV64IMZICOND-NEXT: addiw a0, a0, 6
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_
diff 8:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 14
+; RV32IXQCI-NEXT: qc.selectinei a0, 0, a1, 6
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 14, i32 6
ret i32 %ret
}
@@ -2255,6 +2705,12 @@ define i32 @select_cst_
diff 8_invert(i1 zeroext %cond) {
; RV64IMZICOND-NEXT: slli a0, a0, 3
; RV64IMZICOND-NEXT: addiw a0, a0, 6
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_
diff 8_invert:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 6
+; RV32IXQCI-NEXT: qc.selectinei a0, 0, a1, 14
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 6, i32 14
ret i32 %ret
}
@@ -2298,6 +2754,12 @@ define i32 @select_cst_
diff 1024(i1 zeroext %cond) {
; RV64IMZICOND-NEXT: slli a0, a0, 10
; RV64IMZICOND-NEXT: addiw a0, a0, 6
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_
diff 1024:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 1030
+; RV32IXQCI-NEXT: qc.selectinei a0, 0, a1, 6
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 1030, i32 6
ret i32 %ret
}
@@ -2343,6 +2805,12 @@ define i32 @select_cst_
diff 1024_invert(i1 zeroext %cond) {
; RV64IMZICOND-NEXT: slli a0, a0, 10
; RV64IMZICOND-NEXT: addiw a0, a0, 6
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_
diff 1024_invert:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 1030
+; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a1, 6
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 6, i32 1030
ret i32 %ret
}
@@ -2397,6 +2865,14 @@ define void @select_redundant_czero_eqz1(ptr %0, ptr %1) {
; RV64IMZICOND-NEXT: or a0, a2, a0
; RV64IMZICOND-NEXT: sd a0, 0(a1)
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_redundant_czero_eqz1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
+; RV32IXQCI-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
+; RV32IXQCI-NEXT: qc.mveqi a0, a0, 0, a2
+; RV32IXQCI-NEXT: sw a0, 0(a1)
+; RV32IXQCI-NEXT: ret
entry:
%3 = icmp eq ptr %0, null
%4 = select i1 %3, ptr @select_redundant_czero_eqz_data, ptr %0
@@ -2451,6 +2927,14 @@ define void @select_redundant_czero_eqz2(ptr %0, ptr %1) {
; RV64IMZICOND-NEXT: or a0, a0, a2
; RV64IMZICOND-NEXT: sd a0, 0(a1)
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_redundant_czero_eqz2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
+; RV32IXQCI-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a0
+; RV32IXQCI-NEXT: sw a2, 0(a1)
+; RV32IXQCI-NEXT: ret
entry:
%3 = icmp ne ptr %0, null
%4 = select i1 %3, ptr %0, ptr @select_redundant_czero_eqz_data
diff --git a/llvm/test/CodeGen/RISCV/xqcicli.ll b/llvm/test/CodeGen/RISCV/xqcicli.ll
index b0d51429556ef..8b976163351ae 100644
--- a/llvm/test/CodeGen/RISCV/xqcicli.ll
+++ b/llvm/test/CodeGen/RISCV/xqcicli.ll
@@ -2,10 +2,10 @@
; Test that we are able to generate the Xqcicli instructions
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32I
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli,+experimental-xqcics -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=RV32IXQCICLI
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli,+experimental-xqcicm -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCICLI
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eq:
@@ -20,6 +20,11 @@ define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lieq a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieq a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %b, %x
%sel = select i1 %cmp, i32 11, i32 %a
@@ -39,6 +44,11 @@ define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.line a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ne:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.line a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %b, %x
%sel = select i1 %cmp, i32 11, i32 %a
@@ -58,6 +68,11 @@ define i32 @select_cc_example_slt(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lilt a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slt:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lilt a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %b, %x
%sel = select i1 %cmp, i32 11, i32 %a
@@ -77,6 +92,11 @@ define i32 @select_cc_example_sge(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lige a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sge:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lige a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %b, %x
%sel = select i1 %cmp, i32 11, i32 %a
@@ -96,6 +116,11 @@ define i32 @select_cc_example_uge(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligeu a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_uge:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligeu a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %b, %x
%sel = select i1 %cmp, i32 11, i32 %a
@@ -115,6 +140,11 @@ define i32 @select_cc_example_ult(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.liltu a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ult:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.liltu a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %b, %x
%sel = select i1 %cmp, i32 11, i32 %a
@@ -134,6 +164,11 @@ define i32 @select_cc_example_eq_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.line a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.line a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %b, %x
%sel = select i1 %cmp, i32 %a, i32 11
@@ -153,6 +188,11 @@ define i32 @select_cc_example_ne_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lieq a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ne_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieq a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %b, %x
%sel = select i1 %cmp, i32 %a, i32 11
@@ -172,6 +212,11 @@ define i32 @select_cc_example_slt_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lige a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slt_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lige a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %b, %x
%sel = select i1 %cmp, i32 %a, i32 11
@@ -191,6 +236,11 @@ define i32 @select_cc_example_sge_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lilt a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sge_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lilt a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %b, %x
%sel = select i1 %cmp, i32 %a, i32 11
@@ -210,6 +260,11 @@ define i32 @select_cc_example_uge_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.liltu a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_uge_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.liltu a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %b, %x
%sel = select i1 %cmp, i32 %a, i32 11
@@ -229,6 +284,11 @@ define i32 @select_cc_example_ult_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligeu a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ult_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligeu a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %b, %x
%sel = select i1 %cmp, i32 %a, i32 11
@@ -249,6 +309,11 @@ define i32 @select_cc_example_eqi(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lieqi a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eqi:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieqi a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %b, 12
%sel = select i1 %cmp, i32 11, i32 %a
@@ -269,6 +334,11 @@ define i32 @select_cc_example_nei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.linei a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_nei:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.linei a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %b, 12
%sel = select i1 %cmp, i32 11, i32 %a
@@ -289,6 +359,11 @@ define i32 @select_cc_example_slti(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lilti a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slti:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lilti a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %b, 12
%sel = select i1 %cmp, i32 11, i32 %a
@@ -309,6 +384,11 @@ define i32 @select_cc_example_sgei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligei a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sgei:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligei a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %b, 12
%sel = select i1 %cmp, i32 11, i32 %a
@@ -329,6 +409,11 @@ define i32 @select_cc_example_ulti(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.liltui a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ulti:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.liltui a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %b, 12
%sel = select i1 %cmp, i32 11, i32 %a
@@ -349,6 +434,11 @@ define i32 @select_cc_example_ugei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligeui a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ugei:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligeui a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %b, 12
%sel = select i1 %cmp, i32 11, i32 %a
@@ -369,6 +459,11 @@ define i32 @select_cc_example_eqi_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lieqi a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eqi_c1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieqi a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 12, %b
%sel = select i1 %cmp, i32 11, i32 %a
@@ -389,6 +484,11 @@ define i32 @select_cc_example_nei_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.linei a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_nei_c1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.linei a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 12, %b
%sel = select i1 %cmp, i32 11, i32 %a
@@ -409,6 +509,11 @@ define i32 @select_cc_example_slti_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligei a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slti_c1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligei a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 12, %b
%sel = select i1 %cmp, i32 11, i32 %a
@@ -429,6 +534,11 @@ define i32 @select_cc_example_sgei_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lilti a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sgei_c1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lilti a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 12, %b
%sel = select i1 %cmp, i32 11, i32 %a
@@ -449,6 +559,11 @@ define i32 @select_cc_example_ulti_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligeui a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ulti_c1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligeui a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 12, %b
%sel = select i1 %cmp, i32 11, i32 %a
@@ -469,6 +584,11 @@ define i32 @select_cc_example_ugei_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.liltui a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ugei_c1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.liltui a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 12, %b
%sel = select i1 %cmp, i32 11, i32 %a
@@ -489,6 +609,11 @@ define i32 @select_cc_example_eqi_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.linei a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eqi_c2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.linei a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 12, %b
%sel = select i1 %cmp, i32 %a, i32 11
@@ -509,6 +634,11 @@ define i32 @select_cc_example_nei_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lieqi a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_nei_c2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieqi a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 12, %b
%sel = select i1 %cmp, i32 %a, i32 11
@@ -529,6 +659,11 @@ define i32 @select_cc_example_slti_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lilti a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slti_c2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lilti a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 12, %b
%sel = select i1 %cmp, i32 %a, i32 11
@@ -549,6 +684,11 @@ define i32 @select_cc_example_sgei_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligei a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sgei_c2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligei a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 12, %b
%sel = select i1 %cmp, i32 %a, i32 11
@@ -569,6 +709,11 @@ define i32 @select_cc_example_ulti_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.liltui a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ulti_c2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.liltui a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 12, %b
%sel = select i1 %cmp, i32 %a, i32 11
@@ -589,6 +734,11 @@ define i32 @select_cc_example_ugei_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligeui a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ugei_c2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligeui a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 12, %b
%sel = select i1 %cmp, i32 %a, i32 11
@@ -609,6 +759,11 @@ define i32 @select_cc_example_eqi_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.linei a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eqi_c3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.linei a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %b, 12
%sel = select i1 %cmp, i32 %a, i32 11
@@ -629,6 +784,11 @@ define i32 @select_cc_example_nei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lieqi a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_nei_c3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieqi a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %b, 12
%sel = select i1 %cmp, i32 %a, i32 11
@@ -649,6 +809,11 @@ define i32 @select_cc_example_slti_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligei a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slti_c3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligei a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %b, 12
%sel = select i1 %cmp, i32 %a, i32 11
@@ -669,6 +834,11 @@ define i32 @select_cc_example_sgei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lilti a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sgei_c3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lilti a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %b, 12
%sel = select i1 %cmp, i32 %a, i32 11
@@ -689,6 +859,11 @@ define i32 @select_cc_example_ulti_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligeui a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ulti_c3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligeui a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %b, 12
%sel = select i1 %cmp, i32 %a, i32 11
@@ -709,6 +884,11 @@ define i32 @select_cc_example_ugei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.liltui a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ugei_c3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.liltui a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %b, 12
%sel = select i1 %cmp, i32 %a, i32 11
diff --git a/llvm/test/CodeGen/RISCV/xqcicm.ll b/llvm/test/CodeGen/RISCV/xqcicm.ll
index 56fc864f8ccdc..1741be742323d 100644
--- a/llvm/test/CodeGen/RISCV/xqcicm.ll
+++ b/llvm/test/CodeGen/RISCV/xqcicm.ll
@@ -4,6 +4,10 @@
; RUN: | FileCheck %s --check-prefixes=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCICM
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCICM
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
define i32 @select_example(i32 %cond, i32 %x, i32 %y) {
; RV32I-LABEL: select_example:
@@ -19,9 +23,16 @@ define i32 @select_example(i32 %cond, i32 %x, i32 %y) {
; RV32IXQCICM-LABEL: select_example:
; RV32IXQCICM: # %bb.0: # %entry
; RV32IXQCICM-NEXT: andi a0, a0, 1
-; RV32IXQCICM-NEXT: qc.mveqi a1, a0, 0, a2
-; RV32IXQCICM-NEXT: mv a0, a1
+; RV32IXQCICM-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_example:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cond_trunc = trunc i32 %cond to i1
%sel = select i1 %cond_trunc, i32 %x, i32 %y
@@ -44,6 +55,12 @@ define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mveqi a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mveqi a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -66,6 +83,12 @@ define i32 @select_cc_example_eq1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mveqi a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mveqi a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -88,6 +111,12 @@ define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvnei a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ne:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvnei a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -110,6 +139,12 @@ define i32 @select_cc_example_ne1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvnei a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ne1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvnei a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -132,6 +167,12 @@ define i32 @select_cc_example_slt(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slt:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvlti a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -151,9 +192,15 @@ define i32 @select_cc_example_slt1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_slt1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 12, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 12, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slt1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgei a3, a0, 12, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -176,6 +223,12 @@ define i32 @select_cc_example_sle(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 12, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sle:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvlti a3, a0, 12, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sle i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -195,9 +248,15 @@ define i32 @select_cc_example_sle1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sle1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 11, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 11, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sle1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgei a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sle i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -217,9 +276,15 @@ define i32 @select_cc_example_sgt(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sgt:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 12, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 12, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sgt:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgei a3, a0, 12, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sgt i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -242,6 +307,12 @@ define i32 @select_cc_example_sgt1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sgt1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvlti a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sgt i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -261,9 +332,15 @@ define i32 @select_cc_example_sge(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sge:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 11, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 11, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sge:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgei a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -286,6 +363,12 @@ define i32 @select_cc_example_sge1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 12, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sge1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvlti a3, a0, 12, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -308,6 +391,12 @@ define i32 @select_cc_example_ule(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 12, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ule:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvltui a3, a0, 12, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -327,9 +416,15 @@ define i32 @select_cc_example_ule1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ule1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 11, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 11, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ule1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -349,9 +444,15 @@ define i32 @select_cc_example_ugt(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ugt:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 12, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 12, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ugt:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 12, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ugt i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -374,6 +475,12 @@ define i32 @select_cc_example_ugt1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ugt1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvltui a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ugt i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -396,6 +503,12 @@ define i32 @select_cc_example_ult(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ult:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvltui a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -415,9 +528,15 @@ define i32 @select_cc_example_ult1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ult1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 12, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 12, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ult1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 12, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -437,9 +556,15 @@ define i32 @select_cc_example_uge(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_uge:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 11, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 11, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_uge:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -462,6 +587,12 @@ define i32 @select_cc_example_uge1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 12, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_uge1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvltui a3, a0, 12, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -483,6 +614,12 @@ define i32 @select_cc_example_eq_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mveq a3, a0, a1, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mveq a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -504,6 +641,12 @@ define i32 @select_cc_example_ne_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvne a3, a0, a1, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ne_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvne a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -525,6 +668,12 @@ define i32 @select_cc_example_slt_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvlt a3, a0, a1, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slt_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvlt a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -543,9 +692,15 @@ define i32 @select_cc_example_sge_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sge_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlt a2, a0, a1, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mvge a3, a0, a1, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sge_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvge a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -567,6 +722,12 @@ define i32 @select_cc_example_sgt_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvlt a3, a1, a0, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sgt_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvlt a3, a1, a0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sgt i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -585,9 +746,15 @@ define i32 @select_cc_example_sle_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sle_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlt a2, a1, a0, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mvge a3, a1, a0, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sle_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvge a3, a1, a0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sle i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -609,6 +776,12 @@ define i32 @select_cc_example_ugt_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvltu a3, a1, a0, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ugt_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvltu a3, a1, a0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ugt i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -630,6 +803,12 @@ define i32 @select_cc_example_ult_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvltu a3, a0, a1, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ult_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvltu a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -648,9 +827,15 @@ define i32 @select_cc_example_uge_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_uge_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltu a2, a0, a1, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mvgeu a3, a0, a1, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_uge_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgeu a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -669,9 +854,15 @@ define i32 @select_cc_example_ule_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ule_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltu a2, a1, a0, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mvgeu a3, a1, a0, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ule_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgeu a3, a1, a0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -695,6 +886,13 @@ define i32 @select_cc_example_ule_neg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvltu a3, a0, a1, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ule_neg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: li a1, -10
+; RV32IXQCI-NEXT: qc.mvltu a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 %a, -11
%sel = select i1 %cmp, i32 %x, i32 %y
diff --git a/llvm/test/CodeGen/RISCV/xqcics.ll b/llvm/test/CodeGen/RISCV/xqcics.ll
index 0e90b1fda0ea2..38de8fbd78b36 100644
--- a/llvm/test/CodeGen/RISCV/xqcics.ll
+++ b/llvm/test/CodeGen/RISCV/xqcics.ll
@@ -5,7 +5,9 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCICS
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics,+experimental-xqcicm -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=RV32IXQCICS
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCICM
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
define i32 @select_cc_example_eq_s1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eq_s1:
@@ -23,6 +25,18 @@ define i32 @select_cc_example_eq_s1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: andi a0, a0, 1
; RV32IXQCICS-NEXT: qc.selectinei a0, 0, a2, 12
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_eq_s1:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: andi a0, a0, 1
+; RV32IXQCICM-NEXT: qc.selectinei a0, 0, a2, 12
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq_s1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.selectinei a0, 0, a2, 12
+; RV32IXQCI-NEXT: ret
entry:
%cond_trunc = trunc i32 %a to i1
%sel = select i1 %cond_trunc, i32 %x, i32 12
@@ -46,6 +60,18 @@ define i32 @select_cc_example_eq_s2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: andi a0, a0, 1
; RV32IXQCICS-NEXT: qc.selectieqi a0, 0, a2, 12
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_eq_s2:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: andi a0, a0, 1
+; RV32IXQCICM-NEXT: qc.selectieqi a0, 0, a2, 12
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq_s2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a2, 12
+; RV32IXQCI-NEXT: ret
entry:
%cond_trunc = trunc i32 %a to i1
%sel = select i1 %cond_trunc, i32 12, i32 %x
@@ -70,6 +96,20 @@ define i32 @select_cc_example_eq_s3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: li a1, 25
; RV32IXQCICS-NEXT: qc.selectieqi a0, 0, a1, 12
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_eq_s3:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: andi a0, a0, 1
+; RV32IXQCICM-NEXT: li a1, 25
+; RV32IXQCICM-NEXT: qc.selectieqi a0, 0, a1, 12
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq_s3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: li a1, 25
+; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a1, 12
+; RV32IXQCI-NEXT: ret
entry:
%cond_trunc = trunc i32 %a to i1
%sel = select i1 %cond_trunc, i32 12, i32 25
@@ -91,6 +131,18 @@ define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selecteqi a0, 11, a2, a3
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_eq:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mveqi a3, a0, 11, a2
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mveqi a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -112,6 +164,18 @@ define i32 @select_cc_example_eq_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selecteqi a0, 11, a2, a3
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_eq_c:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mveqi a3, a0, 11, a2
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mveqi a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -133,6 +197,18 @@ define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectnei a0, 11, a2, a3
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_ne:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvnei a3, a0, 11, a2
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ne:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvnei a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -154,6 +230,18 @@ define i32 @select_cc_example_ne_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectnei a0, 11, a2, a3
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_ne_c:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvnei a3, a0, 11, a2
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ne_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvnei a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -174,6 +262,17 @@ define i32 @select_cc_example_eqi(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieq a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_eqi:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectieq a0, a1, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eqi:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.line a2, a0, a1, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 11
@@ -194,6 +293,17 @@ define i32 @select_cc_example_eqi_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectine a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_eqi_c:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectine a0, a1, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eqi_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieq a2, a0, a1, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, %b
%sel = select i1 %cmp, i32 11, i32 %x
@@ -214,6 +324,17 @@ define i32 @select_cc_example_nei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectine a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_nei:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectine a0, a1, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_nei:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieq a2, a0, a1, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 11
@@ -234,6 +355,17 @@ define i32 @select_cc_example_nei_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieq a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_nei_c:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectieq a0, a1, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_nei_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.line a2, a0, a1, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, %b
%sel = select i1 %cmp, i32 11, i32 %x
@@ -255,6 +387,17 @@ define i32 @select_cc_example_ieqi(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_ieqi:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectieqi a0, 12, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ieqi:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 12
%sel = select i1 %cmp, i32 %x, i32 11
@@ -276,6 +419,17 @@ define i32 @select_cc_example_ieqi_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_ieqi_c1:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectieqi a0, 12, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ieqi_c1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 12, %a
%sel = select i1 %cmp, i32 %x, i32 11
@@ -297,6 +451,17 @@ define i32 @select_cc_example_ieqi_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_ieqi_c2:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectinei a0, 12, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ieqi_c2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 12
%sel = select i1 %cmp, i32 11, i32 %x
@@ -318,6 +483,17 @@ define i32 @select_cc_example_ieqi_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_ieqi_c3:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectinei a0, 12, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ieqi_c3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 12, %a
%sel = select i1 %cmp, i32 11, i32 %x
@@ -339,6 +515,17 @@ define i32 @select_cc_example_inei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_inei:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectinei a0, 12, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_inei:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, 12
%sel = select i1 %cmp, i32 %x, i32 11
@@ -360,6 +547,17 @@ define i32 @select_cc_example_inei_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_inei_c1:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectinei a0, 12, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_inei_c1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 12, %a
%sel = select i1 %cmp, i32 %x, i32 11
@@ -381,6 +579,17 @@ define i32 @select_cc_example_inei_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_inei_c2:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectieqi a0, 12, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_inei_c2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, 12
%sel = select i1 %cmp, i32 11, i32 %x
@@ -402,6 +611,17 @@ define i32 @select_cc_example_inei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_inei_c3:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectieqi a0, 12, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_inei_c3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 12, %a
%sel = select i1 %cmp, i32 11, i32 %x
@@ -423,6 +643,16 @@ define i32 @select_cc_example_eqii(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectiieq a0, a1, 13, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_eqii:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectiieq a0, a1, 13, 11
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eqii:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.selectiieq a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, %b
%sel = select i1 %cmp, i32 13, i32 11
@@ -444,6 +674,16 @@ define i32 @select_cc_example_neii(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectiine a0, a1, 13, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCICM-LABEL: select_cc_example_neii:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectiine a0, a1, 13, 11
+; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_neii:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.selectiine a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, %b
%sel = select i1 %cmp, i32 13, i32 11
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