[llvm] a3f901f - [RISCV] Update floating point load latency in SiFive7 scheduling model (#159462)
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Thu Sep 18 13:27:40 PDT 2025
Author: Min-Yih Hsu
Date: 2025-09-18T13:27:36-07:00
New Revision: a3f901f70a028bf369586b6ab561371a63922ce0
URL: https://github.com/llvm/llvm-project/commit/a3f901f70a028bf369586b6ab561371a63922ce0
DIFF: https://github.com/llvm/llvm-project/commit/a3f901f70a028bf369586b6ab561371a63922ce0.diff
LOG: [RISCV] Update floating point load latency in SiFive7 scheduling model (#159462)
The latency of floating point loads in SiFive7 should be the same as
their integer counterparts.
Co-authored-by: Michael Maitland <michaeltmaitland at gmail.com>
Added:
llvm/test/tools/llvm-mca/RISCV/SiFive7/scalar-load-store.s
Modified:
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index ddb6427ff3366..d1d5a27da40f0 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -362,16 +362,14 @@ multiclass SiFive7WriteResBase<int VLEN,
def : WriteRes<WriteFST64, [PipeA]>;
let Latency = 3 in {
- def : WriteRes<WriteLDB, [PipeA]>;
- def : WriteRes<WriteLDH, [PipeA]>;
- def : WriteRes<WriteLDW, [PipeA]>;
- def : WriteRes<WriteLDD, [PipeA]>;
- }
-
- let Latency = 2 in {
- def : WriteRes<WriteFLD16, [PipeA]>;
- def : WriteRes<WriteFLD32, [PipeA]>;
- def : WriteRes<WriteFLD64, [PipeA]>;
+ def : WriteRes<WriteLDB, [PipeA]>;
+ def : WriteRes<WriteLDH, [PipeA]>;
+ def : WriteRes<WriteLDW, [PipeA]>;
+ def : WriteRes<WriteLDD, [PipeA]>;
+
+ def : WriteRes<WriteFLD16, [PipeA]>;
+ def : WriteRes<WriteFLD32, [PipeA]>;
+ def : WriteRes<WriteFLD64, [PipeA]>;
}
// Atomic memory
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/scalar-load-store.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/scalar-load-store.s
new file mode 100644
index 0000000000000..01fe46244b558
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/scalar-load-store.s
@@ -0,0 +1,82 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -instruction-tables=full -iterations=1 < %s \
+# RUN: | FileCheck %s
+
+lh t0, 0(sp)
+flh fa0, 0(sp)
+lw t2, 0(sp)
+flw fa2, 0(sp)
+ld t4, 0(sp)
+fld fa4, 0(sp)
+
+sh t1, 0(sp)
+fsh fa1, 0(sp)
+sw t3, 0(sp)
+fsw fa3, 0(sp)
+sd t5, 0(sp)
+fsd fa5, 0(sp)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - VLEN512SiFive7FDiv:1
+# CHECK-NEXT: [1] - VLEN512SiFive7IDiv:1
+# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1
+# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
+# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1
+# CHECK-NEXT: [5] - VLEN512SiFive7VA:1
+# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1
+# CHECK-NEXT: [7] - VLEN512SiFive7VL:1
+# CHECK-NEXT: [8] - VLEN512SiFive7VS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB LH lh t0, 0(sp)
+# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB FLH flh fa0, 0(sp)
+# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_LWSP lw t2, 0(sp)
+# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB FLW flw fa2, 0(sp)
+# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_LDSP ld t4, 0(sp)
+# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_FLDSP fld fa4, 0(sp)
+# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB SH sh t1, 0(sp)
+# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB FSH fsh fa1, 0(sp)
+# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_SWSP sw t3, 0(sp)
+# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB FSW fsw fa3, 0(sp)
+# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_SDSP sd t5, 0(sp)
+# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_FSDSP fsd fa5, 0(sp)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
+# CHECK-NEXT: [1] - VLEN512SiFive7IDiv
+# CHECK-NEXT: [2] - VLEN512SiFive7PipeA
+# CHECK-NEXT: [3] - VLEN512SiFive7PipeB
+# CHECK-NEXT: [4] - VLEN512SiFive7VA
+# CHECK-NEXT: [5] - VLEN512SiFive7VCQ
+# CHECK-NEXT: [6] - VLEN512SiFive7VL
+# CHECK-NEXT: [7] - VLEN512SiFive7VS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# CHECK-NEXT: - - 12.00 - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - lh t0, 0(sp)
+# CHECK-NEXT: - - 1.00 - - - - - flh fa0, 0(sp)
+# CHECK-NEXT: - - 1.00 - - - - - lw t2, 0(sp)
+# CHECK-NEXT: - - 1.00 - - - - - flw fa2, 0(sp)
+# CHECK-NEXT: - - 1.00 - - - - - ld t4, 0(sp)
+# CHECK-NEXT: - - 1.00 - - - - - fld fa4, 0(sp)
+# CHECK-NEXT: - - 1.00 - - - - - sh t1, 0(sp)
+# CHECK-NEXT: - - 1.00 - - - - - fsh fa1, 0(sp)
+# CHECK-NEXT: - - 1.00 - - - - - sw t3, 0(sp)
+# CHECK-NEXT: - - 1.00 - - - - - fsw fa3, 0(sp)
+# CHECK-NEXT: - - 1.00 - - - - - sd t5, 0(sp)
+# CHECK-NEXT: - - 1.00 - - - - - fsd fa5, 0(sp)
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