[llvm] 70a7ffd - [LV] Add missing test cover for replicating load/store costs.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 18 11:47:35 PDT 2025
Author: Florian Hahn
Date: 2025-09-18T19:47:06+01:00
New Revision: 70a7ffdc290ab466c2394d22f38c0368ce5266d1
URL: https://github.com/llvm/llvm-project/commit/70a7ffdc290ab466c2394d22f38c0368ce5266d1
DIFF: https://github.com/llvm/llvm-project/commit/70a7ffdc290ab466c2394d22f38c0368ce5266d1.diff
LOG: [LV] Add missing test cover for replicating load/store costs.
Added:
llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
new file mode 100644
index 0000000000000..10975a84c680f
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
@@ -0,0 +1,342 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "scalar.ph:" --version 6
+; RUN: opt -p loop-vectorize -S %s | FileCheck %s
+
+target triple = "arm64-apple-macosx15.0.0"
+
+define void @replicating_load_used_as_store_addr(ptr noalias %A) {
+; CHECK-LABEL: define void @replicating_load_used_as_store_addr(
+; CHECK-SAME: ptr noalias [[A:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP0]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr ptr, ptr [[A]], i64 [[INDEX]]
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr ptr, ptr [[A]], i64 [[TMP0]]
+; CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP3]], align 8
+; CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP4]], align 8
+; CHECK-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP1]] to i32
+; CHECK-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP2]] to i32
+; CHECK-NEXT: store i32 [[TMP7]], ptr [[TMP5]], align 4
+; CHECK-NEXT: store i32 [[TMP8]], ptr [[TMP6]], align 4
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
+; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[SCALAR_PH:.*]]
+; CHECK: [[SCALAR_PH]]:
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %iv.next = add i64 %iv, 1
+ %gep.A = getelementptr ptr, ptr %A, i64 %iv
+ %l.p = load ptr, ptr %gep.A, align 8
+ %iv.trunc = trunc i64 %iv.next to i32
+ store i32 %iv.trunc, ptr %l.p, align 4
+ %ec = icmp eq i64 %iv, 100
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @replicating_load_used_as_store_addr_2(ptr noalias %invar.dst, ptr noalias %invar.src, ptr noalias %src) {
+; CHECK-LABEL: define void @replicating_load_used_as_store_addr_2(
+; CHECK-SAME: ptr noalias [[INVAR_DST:%.*]], ptr noalias [[INVAR_SRC:%.*]], ptr noalias [[SRC:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[INVAR_SRC]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[TMP0]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i128, ptr [[SRC]], i64 [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], 123
+; CHECK-NEXT: store i32 [[TMP4]], ptr [[INVAR_DST]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
+; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br [[EXIT:label %.*]]
+; CHECK: [[SCALAR_PH:.*:]]
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %l.offset = load i32, ptr %invar.src, align 4
+ %offset.ext = sext i32 %l.offset to i64
+ %gep.src = getelementptr i128, ptr %src, i64 %offset.ext
+ %l.v = load i32, ptr %gep.src, align 4
+ %add = add i32 %l.v, 123
+ store i32 %add, ptr %invar.dst, align 8
+ %iv.next = add i64 %iv, 1
+ %exitcond41.not = icmp eq i64 %iv.next, 100
+ br i1 %exitcond41.not, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+
+define void @replicating_load_used_as_store_addr_3(ptr noalias %src, ptr noalias %dst, ptr noalias %invar.dst, i8 %x) {
+; CHECK-LABEL: define void @replicating_load_used_as_store_addr_3(
+; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], ptr noalias [[INVAR_DST:%.*]], i8 [[X:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i8 [[X]], 10
+; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP1]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 1
+; CHECK-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i32
+; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], 111
+; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP4]] to i64
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP6]]
+; CHECK-NEXT: store i8 0, ptr [[TMP7]], align 1
+; CHECK-NEXT: store i8 0, ptr [[TMP7]], align 1
+; CHECK-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP5]] to i8
+; CHECK-NEXT: store i8 [[TMP8]], ptr [[INVAR_DST]], align 1
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
+; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br [[EXIT:label %.*]]
+; CHECK: [[SCALAR_PH:.*:]]
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %xor = xor i8 %x, 10
+ %ext = zext i8 %xor to i64
+ %gep.src = getelementptr i8, ptr %src, i64 %ext
+ %l = load i8, ptr %gep.src, align 1
+ %l.ext = zext i8 %l to i32
+ %xor.2 = xor i32 %l.ext, 111
+ %idx2.ext = zext i32 %l.ext to i64
+ %gep.dst = getelementptr i8, ptr %dst, i64 %idx2.ext
+ store i8 0, ptr %gep.dst, align 1
+ %xor.2.trunc = trunc i32 %xor.2 to i8
+ store i8 %xor.2.trunc, ptr %invar.dst, align 1
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv.next, 100
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @uniform_gep_for_replicating_gep(ptr %dst) {
+; CHECK-LABEL: define void @uniform_gep_for_replicating_gep(
+; CHECK-SAME: ptr [[DST:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ <i32 0, i32 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[STEP_ADD:%.*]] = add <2 x i32> [[VEC_IND]], splat (i32 2)
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[INDEX]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[INDEX]], 3
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <2 x i32> [[VEC_IND]], zeroinitializer
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <2 x i32> [[STEP_ADD]], zeroinitializer
+; CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP0]], 1
+; CHECK-NEXT: [[TMP7:%.*]] = lshr i32 [[TMP1]], 1
+; CHECK-NEXT: [[TMP8:%.*]] = lshr i32 [[TMP2]], 1
+; CHECK-NEXT: [[TMP9:%.*]] = lshr i32 [[TMP3]], 1
+; CHECK-NEXT: [[TMP10:%.*]] = zext <2 x i1> [[TMP4]] to <2 x i8>
+; CHECK-NEXT: [[TMP11:%.*]] = zext <2 x i1> [[TMP5]] to <2 x i8>
+; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP6]] to i64
+; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP7]] to i64
+; CHECK-NEXT: [[TMP14:%.*]] = zext i32 [[TMP8]] to i64
+; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP9]] to i64
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP12]]
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP13]]
+; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP14]]
+; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP15]]
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <2 x i8> [[TMP10]], i32 0
+; CHECK-NEXT: store i8 [[TMP20]], ptr [[TMP16]], align 1
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <2 x i8> [[TMP10]], i32 1
+; CHECK-NEXT: store i8 [[TMP21]], ptr [[TMP17]], align 1
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <2 x i8> [[TMP11]], i32 0
+; CHECK-NEXT: store i8 [[TMP22]], ptr [[TMP18]], align 1
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <2 x i8> [[TMP11]], i32 1
+; CHECK-NEXT: store i8 [[TMP23]], ptr [[TMP19]], align 1
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i32> [[STEP_ADD]], splat (i32 2)
+; CHECK-NEXT: [[TMP24:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; CHECK-NEXT: br i1 [[TMP24]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[SCALAR_PH:.*]]
+; CHECK: [[SCALAR_PH]]:
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
+ %c = icmp eq i32 %iv, 0
+ %shift = lshr i32 %iv, 1
+ %ext = zext i1 %c to i8
+ %ext.shift = zext i32 %shift to i64
+ %gep = getelementptr i64, ptr %dst, i64 %ext.shift
+ store i8 %ext, ptr %gep, align 1
+ %iv.next = add i32 %iv, 1
+ %ec = icmp eq i32 %iv, 128
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @test_load_gep_widen_induction(ptr noalias %dst, ptr noalias %dst2) #0 {
+; CHECK-LABEL: define void @test_load_gep_widen_induction(
+; CHECK-SAME: ptr noalias [[DST:%.*]], ptr noalias [[DST2:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[OFFSET_IDX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[STEP_ADD:%.*]] = add <2 x i64> [[VEC_IND]], splat (i64 2)
+; CHECK-NEXT: [[STEP_ADD_2:%.*]] = add <2 x i64> [[STEP_ADD]], splat (i64 2)
+; CHECK-NEXT: [[STEP_ADD_3:%.*]] = add <2 x i64> [[STEP_ADD_2]], splat (i64 2)
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i128, ptr [[DST]], <2 x i64> [[VEC_IND]]
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i128, ptr [[DST]], <2 x i64> [[STEP_ADD]]
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i128, ptr [[DST]], <2 x i64> [[STEP_ADD_2]]
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i128, ptr [[DST]], <2 x i64> [[STEP_ADD_3]]
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x ptr> [[TMP0]], i32 0
+; CHECK-NEXT: store ptr null, ptr [[TMP4]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x ptr> [[TMP0]], i32 1
+; CHECK-NEXT: store ptr null, ptr [[TMP5]], align 8
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x ptr> [[TMP1]], i32 0
+; CHECK-NEXT: store ptr null, ptr [[TMP6]], align 8
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x ptr> [[TMP1]], i32 1
+; CHECK-NEXT: store ptr null, ptr [[TMP7]], align 8
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x ptr> [[TMP2]], i32 0
+; CHECK-NEXT: store ptr null, ptr [[TMP8]], align 8
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x ptr> [[TMP2]], i32 1
+; CHECK-NEXT: store ptr null, ptr [[TMP9]], align 8
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x ptr> [[TMP3]], i32 0
+; CHECK-NEXT: store ptr null, ptr [[TMP10]], align 8
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x ptr> [[TMP3]], i32 1
+; CHECK-NEXT: store ptr null, ptr [[TMP11]], align 8
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr ptr, ptr [[DST2]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr ptr, ptr [[TMP12]], i32 2
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr ptr, ptr [[TMP12]], i32 4
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr ptr, ptr [[TMP12]], i32 6
+; CHECK-NEXT: store <2 x ptr> [[TMP0]], ptr [[TMP12]], align 8
+; CHECK-NEXT: store <2 x ptr> [[TMP1]], ptr [[TMP13]], align 8
+; CHECK-NEXT: store <2 x ptr> [[TMP2]], ptr [[TMP14]], align 8
+; CHECK-NEXT: store <2 x ptr> [[TMP3]], ptr [[TMP15]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[OFFSET_IDX]], 8
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[STEP_ADD_3]], splat (i64 2)
+; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96
+; CHECK-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[SCALAR_PH:.*]]
+; CHECK: [[SCALAR_PH]]:
+;
+entry:
+ br label %loop
+
+loop: ; preds = %loop, %entry
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %gep.dst.iv = getelementptr i128, ptr %dst, i64 %iv
+ %iv.next = add i64 %iv, 1
+ store ptr null, ptr %gep.dst.iv, align 8
+ %gep.dst2.iv = getelementptr ptr, ptr %dst2, i64 %iv
+ store ptr %gep.dst.iv, ptr %gep.dst2.iv
+ %exitcond.not = icmp eq i64 %iv.next, 100
+ br i1 %exitcond.not, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+
+define ptr @replicating_store_in_conditional_latch(ptr %p, i32 %n) #0 {
+; CHECK-LABEL: define ptr @replicating_store_in_conditional_latch(
+; CHECK-SAME: ptr [[P:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = sub i32 0, [[N]]
+; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP3]], 4
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 4
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[N_MOD_VF]], 0
+; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 4, i64 [[N_MOD_VF]]
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[TMP5]]
+; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i64 [[N_VEC]] to i32
+; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[DOTCAST]], -2
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[N_VEC]], 48
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP7]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 48
+; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 48
+; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 96
+; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 144
+; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[P]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT: [[NEXT_GEP1:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP9]]
+; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP10]]
+; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP11]]
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 24
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[NEXT_GEP1]], i64 24
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 24
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[NEXT_GEP3]], i64 24
+; CHECK-NEXT: store ptr null, ptr [[TMP12]], align 8
+; CHECK-NEXT: store ptr null, ptr [[TMP13]], align 8
+; CHECK-NEXT: store ptr null, ptr [[TMP14]], align 8
+; CHECK-NEXT: store ptr null, ptr [[TMP15]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+;
+entry:
+ br label %loop.header
+
+loop.header:
+ %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
+ %ptr.iv = phi ptr [ %p, %entry ], [ %ptr.iv.next, %loop.latch ]
+ %gep.ptr.iv = getelementptr i8, ptr %ptr.iv, i64 24
+ %c = icmp eq i32 %iv, %n
+ br i1 %c, label %exit, label %loop.latch
+
+loop.latch:
+ %iv.next = add nsw i32 %iv, -2
+ store ptr null, ptr %gep.ptr.iv, align 8
+ %ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 48
+ br label %loop.header
+
+exit:
+ ret ptr %gep.ptr.iv
+}
+
+attributes #0 = { "target-cpu"="neoverse-512tvb" }
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