[llvm] c3383d7 - [RISCV][GlobalIsel] Remove redundant sext.w for ADDIW (#159597)

[via llvm-commits]

Author: Shaoce SUN
Date: 2025-09-18T17:29:54Z
New Revision: c3383d74a735decd70088f382466b4a7d699f948

URL: https://github.com/llvm/llvm-project/commit/c3383d74a735decd70088f382466b4a7d699f948
DIFF: https://github.com/llvm/llvm-project/commit/c3383d74a735decd70088f382466b4a7d699f948.diff

LOG: [RISCV][GlobalIsel] Remove redundant sext.w for ADDIW (#159597)

This is the minimal case generated by clang at `-O0`; I'm not sure if
writing the test this way is appropriate.

Added: 
    llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll

Modified: 
    llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    llvm/lib/Target/RISCV/RISCVGISel.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4330d4e91e0ee..71c21e43998d4 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -226,6 +226,8 @@ bool RISCVInstructionSelector::hasAllNBitUsers(const MachineInstr &MI,
     case RISCV::ADDW:
     case RISCV::ADDIW:
     case RISCV::SUBW:
+    case RISCV::FCVT_D_W:
+    case RISCV::FCVT_S_W:
       if (Bits >= 32)
         break;
       return false;

diff  --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index 791efca09d40e..a9ecf44e8da1e 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -143,6 +143,9 @@ def : Pat<(anyext (i32 GPR:$src)), (COPY GPR:$src)>;
 def : Pat<(sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
 def : Pat<(i32 (trunc GPR:$src)), (COPY GPR:$src)>;
 
+def : Pat<(sext_inreg (i64 (add GPR:$rs1, simm12:$imm)), i32),
+          (ADDIW GPR:$rs1, simm12:$imm)>;
+
 // Use sext if the sign bit of the input is 0.
 def : Pat<(zext_is_sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
 }

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll
new file mode 100644
index 0000000000000..99834f0221673
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV64I
+
+define i32 @addiw_sext_inreg(i32 noundef signext %A) #0 {
+; RV64I-LABEL: addiw_sext_inreg:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:    addiw a0, a0, 123
+; RV64I-NEXT:    ret
+entry:
+  %add = add nsw i32 123, %A
+  ret i32 %add
+}
+
+attributes #0 = { noinline nounwind optnone }