[llvm] [RISCV][GlobalIsel] Remove redundant sext.w for ADDIW (PR #159597)

[Shaoce SUN via llvm-commits]

https://github.com/sunshaoce updated https://github.com/llvm/llvm-project/pull/159597

>From 58e2acaa91b336e9614d1646cc65795d4df7f7f6 Mon Sep 17 00:00:00 2001
From: Shaoce SUN <sunshaoce at outlook.com>
Date: Thu, 18 Sep 2025 23:49:42 +0800
Subject: [PATCH 1/3] Precommit test

---
 .../CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll

diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll
new file mode 100644
index 0000000000000..818bca0be3f19
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV64I
+
+define i32 @addiw_sext_inreg(i32 noundef signext %A) #0 {
+; RV64I-LABEL: addiw_sext_inreg:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:    addiw a0, a0, 123
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    ret
+entry:
+  %add = add nsw i32 123, %A
+  ret i32 %add
+}
+
+attributes #0 = { noinline nounwind optnone }

>From 1cc99434b00e1549bbc1d7b73c6e940fcf30644f Mon Sep 17 00:00:00 2001
From: Shaoce SUN <sunshaoce at outlook.com>
Date: Thu, 18 Sep 2025 23:55:43 +0800
Subject: [PATCH 2/3] Remove sext

---
 llvm/lib/Target/RISCV/RISCVFeatures.td                 | 1 +
 llvm/lib/Target/RISCV/RISCVGISel.td                    | 5 +++++
 llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll | 1 -
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 95703e33926c5..6ae4dda60c8db 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -288,6 +288,7 @@ def FeatureStdExtF
 def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
                  AssemblerPredicate<(all_of FeatureStdExtF),
                                     "'F' (Single-Precision Floating-Point)">;
+def NoStdExtF : Predicate<"!Subtarget->hasStdExtF()">;
 
 def FeatureStdExtD
     : RISCVExtension<2, 2, "Double-Precision Floating-Point",
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index 791efca09d40e..caa0ebf4f7550 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -147,6 +147,11 @@ def : Pat<(i32 (trunc GPR:$src)), (COPY GPR:$src)>;
 def : Pat<(zext_is_sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
 }
 
+let Predicates = [IsRV64, NoStdExtF] in {
+def : Pat<(sext_inreg (i64 (add GPR:$rs1, simm12:$imm)), i32),
+          (ADDIW GPR:$rs1, simm12:$imm)>;
+}
+
 let Predicates = [IsRV64, NoStdExtZba] in
 def : Pat<(zext (i32 GPR:$src)), (SRLI (i64 (SLLI GPR:$src, 32)), 32)>;
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll
index 818bca0be3f19..99834f0221673 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll
@@ -6,7 +6,6 @@ define i32 @addiw_sext_inreg(i32 noundef signext %A) #0 {
 ; RV64I-LABEL: addiw_sext_inreg:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    addiw a0, a0, 123
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 entry:
   %add = add nsw i32 123, %A

>From f553c293be355a437f705dccdd923f5dc0a691f0 Mon Sep 17 00:00:00 2001
From: Shaoce SUN <sunshaoce at outlook.com>
Date: Fri, 19 Sep 2025 00:50:58 +0800
Subject: [PATCH 3/3] Address comment

---
 llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 2 ++
 llvm/lib/Target/RISCV/RISCVGISel.td                      | 8 +++-----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4330d4e91e0ee..71c21e43998d4 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -226,6 +226,8 @@ bool RISCVInstructionSelector::hasAllNBitUsers(const MachineInstr &MI,
     case RISCV::ADDW:
     case RISCV::ADDIW:
     case RISCV::SUBW:
+    case RISCV::FCVT_D_W:
+    case RISCV::FCVT_S_W:
       if (Bits >= 32)
         break;
       return false;
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index caa0ebf4f7550..a9ecf44e8da1e 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -143,13 +143,11 @@ def : Pat<(anyext (i32 GPR:$src)), (COPY GPR:$src)>;
 def : Pat<(sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
 def : Pat<(i32 (trunc GPR:$src)), (COPY GPR:$src)>;
 
-// Use sext if the sign bit of the input is 0.
-def : Pat<(zext_is_sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
-}
-
-let Predicates = [IsRV64, NoStdExtF] in {
 def : Pat<(sext_inreg (i64 (add GPR:$rs1, simm12:$imm)), i32),
           (ADDIW GPR:$rs1, simm12:$imm)>;
+
+// Use sext if the sign bit of the input is 0.
+def : Pat<(zext_is_sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
 }
 
 let Predicates = [IsRV64, NoStdExtZba] in