[llvm] [RISCV][GlobalIsel] Remove redundant sext.w for ADDIW (PR #159597)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Shaoce SUN (sunshaoce)

<details>
<summary>Changes</summary>

This is the minimal case generated by clang at `-O0`; I'm not sure if writing the test this way is appropriate.

---
Full diff: https://github.com/llvm/llvm-project/pull/159597.diff


1 Files Affected:

- (added) llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll (+16) 


``````````diff
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll
new file mode 100644
index 0000000000000..818bca0be3f19
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV64I
+
+define i32 @addiw_sext_inreg(i32 noundef signext %A) #0 {
+; RV64I-LABEL: addiw_sext_inreg:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:    addiw a0, a0, 123
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    ret
+entry:
+  %add = add nsw i32 123, %A
+  ret i32 %add
+}
+
+attributes #0 = { noinline nounwind optnone }

``````````

</details>


https://github.com/llvm/llvm-project/pull/159597