[llvm] [AMDGPU] Remove setcc by using add/sub carryout (PR #155255)

[Matt Arsenault via llvm-commits]

================
@@ -6105,44 +6112,90 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
     unsigned WaveSize = TRI->getRegSizeInBits(*Src2RC);
     assert(WaveSize == 64 || WaveSize == 32);
 
-    if (WaveSize == 64) {
-      if (ST.hasScalarCompareEq64()) {
-        BuildMI(*BB, MII, DL, TII->get(AMDGPU::S_CMP_LG_U64))
-            .addReg(Src2.getReg())
-            .addImm(0);
-      } else {
-        const TargetRegisterClass *SubRC =
-            TRI->getSubRegisterClass(Src2RC, AMDGPU::sub0);
-        MachineOperand Src2Sub0 = TII->buildExtractSubRegOrImm(
-            MII, MRI, Src2, Src2RC, AMDGPU::sub0, SubRC);
-        MachineOperand Src2Sub1 = TII->buildExtractSubRegOrImm(
-            MII, MRI, Src2, Src2RC, AMDGPU::sub1, SubRC);
-        Register Src2_32 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
-
-        BuildMI(*BB, MII, DL, TII->get(AMDGPU::S_OR_B32), Src2_32)
-            .add(Src2Sub0)
-            .add(Src2Sub1);
+    unsigned SelectOpc =
+        (WaveSize == 64) ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32;
+    unsigned AddcSubbOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
+    unsigned AddSubOpc = IsAdd ? AMDGPU::S_ADD_I32 : AMDGPU::S_SUB_I32;
+    //  Lowering for:
+    //
+    //    S_UADDO_PSEUDO|S_ADD_CO_PSEUDO
+    //    <no SCC def code>
+    //    S_ADD_CO_PSEUDO
+    //
+    //  produces:
+    //
+    //    S_ADD_I32|S_ADDC_U32                  ; lowered from S_UADDO_PSEUDO
+    //    SREG = S_CSELECT_B32|64 [1,-1], 0     ; lowered from S_UADDO_PSEUDO
+    //    <no SCC def code>
+    //    S_CMP32|64 SREG, 0                    ; lowered from S_ADD_CO_PSEUDO
+    //    S_ADDC_U32                            ; lowered from S_ADD_CO_PSEUDO
+    //
+    //  At this point before generating the S_CMP check if it is redundant.  If
+    //  so do not recalculate it.  Subsequent optimizations will also delete the
+    //  dead S_CSELECT*.
+
+    bool RecalculateSCC{true};
+    MachineInstr *SelectDef = MRI.getVRegDef(Src2.getReg());
+    if (SelectDef && SelectDef->getParent() == BB &&
----------------
arsenm wrote:

I don't want to have an ad-hoc scan for SCC here. These operations could have been glued in the first place, and this kind of optimization is beyond the scope of what a pseudo expansion should be doing. Plus if you did want to know if scc was clobbered, should use MachineBasicBlock::computeRegisterLiveness 

https://github.com/llvm/llvm-project/pull/155255