[llvm] Enable machine combiner pass for ARM (PR #159466)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/lib/Target/ARM/ARMBaseInstrInfo.h llvm/lib/Target/ARM/ARMTargetMachine.cpp
``````````

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 81174bd5c..378f1c80b 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2648,8 +2648,8 @@ bool ARMBaseInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
   case ARM::tADDrr:
   // FIXME: Unable to reassociate because it expects a rGPR register, but gets a
   // GPRnopc register in reassociation.
-  // Fixing this requires splitting t2ADDrr because it has different rules depending on SP
-  // case ARM::t2ADDrr:
+  // Fixing this requires splitting t2ADDrr because it has different rules
+  // depending on SP case ARM::t2ADDrr:
   case ARM::ANDrr:
   case ARM::tAND:
   case ARM::t2ANDrr:
@@ -3328,11 +3328,10 @@ bool ARMBaseInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
   UseMI.getOperand(1).setIsKill();
   UseMI.getOperand(2).ChangeToImmediate(SOImmValV2);
   DefMI.eraseFromParent();
-  // FIXME: t2ADDrr should be split, as different rules apply when writing to SP.
-  // Just as t2ADDri, that was split to [t2ADDri, t2ADDspImm].
-  // Then the below code will not be needed, as the input/output register
-  // classes will be rgpr or gprSP.
-  // For now, we fix the UseMI operand explicitly here:
+  // FIXME: t2ADDrr should be split, as different rules apply when writing to
+  // SP. Just as t2ADDri, that was split to [t2ADDri, t2ADDspImm]. Then the
+  // below code will not be needed, as the input/output register classes will be
+  // rgpr or gprSP. For now, we fix the UseMI operand explicitly here:
   switch(NewUseOpc){
     case ARM::t2ADDspImm:
     case ARM::t2SUBspImm:

``````````

</details>


https://github.com/llvm/llvm-project/pull/159466