[llvm] Move SI Lower Control Flow Up (PR #159557)
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Thu Sep 18 04:39:07 PDT 2025
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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/Target/AMDGPU/SICustomBranchBundles.h llvm/lib/Target/AMDGPU/SIRestoreNormalEpilog.cpp llvm/lib/Target/AMDGPU/AMDGPU.h llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp llvm/lib/Target/AMDGPU/SILowerControlFlow.h
``````````
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 8210ad88b..d2c1f7f49 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1564,7 +1564,7 @@ void GCNPassConfig::addFastRegAlloc() {
// This must be run immediately after phi elimination and before
// TwoAddressInstructions, otherwise the processing of the tied operand of
// SI_ELSE will introduce a copy of the tied operand source after the else.
- //insertPass(&PHIEliminationID, &SILowerControlFlowLegacyID);
+ // insertPass(&PHIEliminationID, &SILowerControlFlowLegacyID);
insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
@@ -1592,12 +1592,12 @@ void GCNPassConfig::addOptimizedRegAlloc() {
// This must be run immediately after phi elimination and before
// TwoAddressInstructions, otherwise the processing of the tied operand of
// SI_ELSE will introduce a copy of the tied operand source after the else.
- //insertPass(&PHIEliminationID, &SILowerControlFlowLegacyID);
+ // insertPass(&PHIEliminationID, &SILowerControlFlowLegacyID);
if (EnableRewritePartialRegUses)
insertPass(&RenameIndependentSubregsID, &GCNRewritePartialRegUsesID);
-
- insertPass(&RenameIndependentSubregsID,&SIRestoreNormalEpilogLegacyID);
+
+ insertPass(&RenameIndependentSubregsID, &SIRestoreNormalEpilogLegacyID);
if (isPassEnabled(EnablePreRAOptimizations))
insertPass(&MachineSchedulerID, &GCNPreRAOptimizationsID);
@@ -2261,7 +2261,7 @@ void AMDGPUCodeGenPassBuilder::addOptimizedRegAlloc(
// This must be run immediately after phi elimination and before
// TwoAddressInstructions, otherwise the processing of the tied operand of
// SI_ELSE will introduce a copy of the tied operand source after the else.
- //insertPass<PHIEliminationPass>(SILowerControlFlowPass());
+ // insertPass<PHIEliminationPass>(SILowerControlFlowPass());
if (EnableRewritePartialRegUses)
insertPass<RenameIndependentSubregsPass>(GCNRewritePartialRegUsesPass());
diff --git a/llvm/lib/Target/AMDGPU/SICustomBranchBundles.h b/llvm/lib/Target/AMDGPU/SICustomBranchBundles.h
index 0e043b09f..58651c562 100644
--- a/llvm/lib/Target/AMDGPU/SICustomBranchBundles.h
+++ b/llvm/lib/Target/AMDGPU/SICustomBranchBundles.h
@@ -17,9 +17,11 @@ using namespace llvm;
using std::unordered_set;
using std::vector;
-static inline MachineInstr &get_branch_with_dest(MachineBasicBlock &branching_MBB,
- MachineBasicBlock &dest_MBB) {
- auto& TII = *branching_MBB.getParent()->getSubtarget<GCNSubtarget>().getInstrInfo();
+static inline MachineInstr &
+get_branch_with_dest(MachineBasicBlock &branching_MBB,
+ MachineBasicBlock &dest_MBB) {
+ auto &TII =
+ *branching_MBB.getParent()->getSubtarget<GCNSubtarget>().getInstrInfo();
for (MachineInstr &branch_MI : reverse(branching_MBB.instrs()))
if (branch_MI.isBranch() && TII.getBranchDestBlock(branch_MI) == &dest_MBB)
return branch_MI;
@@ -28,10 +30,10 @@ static inline MachineInstr &get_branch_with_dest(MachineBasicBlock &branching_MB
}
static inline void move_ins_before_phis(MachineInstr &MI) {
- MachineBasicBlock& MBB = *MI.getParent();
- MachineFunction& MF = *MBB.getParent();
+ MachineBasicBlock &MBB = *MI.getParent();
+ MachineFunction &MF = *MBB.getParent();
auto &TII = *MF.getSubtarget<GCNSubtarget>().getInstrInfo();
- auto& MRI = MF.getRegInfo();
+ auto &MRI = MF.getRegInfo();
bool phi_seen = false;
MachineBasicBlock::iterator first_phi;
@@ -40,16 +42,16 @@ static inline void move_ins_before_phis(MachineInstr &MI) {
phi_seen = true;
break;
}
-
+
if (!phi_seen) {
MI.removeFromParent();
MBB.insert(MBB.begin(), &MI);
} else {
auto phi = BuildMI(MBB, first_phi, MI.getDebugLoc(), TII.get(AMDGPU::PHI),
- MI.getOperand(0).getReg());
+ MI.getOperand(0).getReg());
for (auto *pred_MBB : MBB.predecessors()) {
Register cloned_reg = MRI.cloneVirtualRegister(MI.getOperand(0).getReg());
- MachineInstr& branch_MI = get_branch_with_dest(*pred_MBB,MBB);
+ MachineInstr &branch_MI = get_branch_with_dest(*pred_MBB, MBB);
MachineInstr *cloned_MI = MF.CloneMachineInstr(&MI);
cloned_MI->getOperand(0).setReg(cloned_reg);
phi.addReg(cloned_reg).addMBB(pred_MBB);
@@ -81,13 +83,13 @@ struct Epilog_Iterator {
++*this;
return to_return;
}
-
};
static inline Epilog_Iterator
-get_epilog_for_successor(MachineBasicBlock& pred_MBB, MachineBasicBlock& succ_MBB) {
- MachineFunction& MF = *pred_MBB.getParent();
- auto& TII = *MF.getSubtarget<GCNSubtarget>().getInstrInfo();
+get_epilog_for_successor(MachineBasicBlock &pred_MBB,
+ MachineBasicBlock &succ_MBB) {
+ MachineFunction &MF = *pred_MBB.getParent();
+ auto &TII = *MF.getSubtarget<GCNSubtarget>().getInstrInfo();
for (MachineInstr &branch_MI : reverse(pred_MBB.instrs()))
if (branch_MI.isBranch() && TII.getBranchDestBlock(branch_MI) == &succ_MBB)
@@ -101,7 +103,7 @@ static inline bool epilogs_are_identical(const vector<MachineInstr *> left,
const MachineBasicBlock &succ_MBB) {
if (left.size() != right.size())
return false;
-
+
for (unsigned i = 0; i < left.size(); i++)
if (!left[i]->isIdenticalTo(*right[i]))
return false;
@@ -109,7 +111,7 @@ static inline bool epilogs_are_identical(const vector<MachineInstr *> left,
}
static inline void move_body(vector<MachineInstr *> &body,
- MachineBasicBlock &dest_MBB) {
+ MachineBasicBlock &dest_MBB) {
for (auto rev_it = body.rbegin(); rev_it != body.rend(); rev_it++) {
MachineInstr &body_ins = **rev_it;
body_ins.removeFromBundle();
@@ -118,20 +120,19 @@ static inline void move_body(vector<MachineInstr *> &body,
}
static inline void normalize_ir_post_phi_elimination(MachineFunction &MF) {
- auto& TII = *MF.getSubtarget<GCNSubtarget>().getInstrInfo();
+ auto &TII = *MF.getSubtarget<GCNSubtarget>().getInstrInfo();
struct CFG_Rewrite_Entry {
unordered_set<MachineBasicBlock *> pred_MBBs;
MachineBasicBlock *succ_MBB;
- vector<MachineInstr*> body;
+ vector<MachineInstr *> body;
};
vector<CFG_Rewrite_Entry> cfg_rewrite_entries;
for (MachineBasicBlock &MBB : MF) {
CFG_Rewrite_Entry to_insert = {{}, &MBB, {}};
for (MachineBasicBlock *pred_MBB : MBB.predecessors()) {
- Epilog_Iterator ep_it =
- get_epilog_for_successor(*pred_MBB, MBB);
+ Epilog_Iterator ep_it = get_epilog_for_successor(*pred_MBB, MBB);
vector<MachineInstr *> epilog;
while (!ep_it.isEnd())
@@ -151,13 +152,13 @@ static inline void normalize_ir_post_phi_elimination(MachineFunction &MF) {
break;
}
- if(!existing_entry_found)
+ if (!existing_entry_found)
cfg_rewrite_entries.push_back(to_insert);
}
to_insert.pred_MBBs.clear();
to_insert.body = epilog;
}
-
+
to_insert.pred_MBBs.insert(pred_MBB);
}
@@ -168,31 +169,31 @@ static inline void normalize_ir_post_phi_elimination(MachineFunction &MF) {
for (MachineBasicBlock *pred_MBB : to_insert.pred_MBBs) {
// Delete instructions that were lowered from epilog
MachineInstr &branch_ins =
- get_branch_with_dest(*pred_MBB, *to_insert.succ_MBB);
+ get_branch_with_dest(*pred_MBB, *to_insert.succ_MBB);
auto epilog_it = ++Epilog_Iterator(branch_ins.getIterator());
while (!epilog_it.isEnd())
epilog_it++->eraseFromBundle();
}
- }
- else if (to_insert.body.size())
+ } else if (to_insert.body.size())
cfg_rewrite_entries.push_back(to_insert);
}
// Perform the journaled rewrites.
for (auto &entry : cfg_rewrite_entries) {
MachineBasicBlock *mezzanine_MBB = MF.CreateMachineBasicBlock();
- MF.insert(MF.end(),mezzanine_MBB);
+ MF.insert(MF.end(), mezzanine_MBB);
// Deal with mezzanine to successor succession.
- BuildMI(mezzanine_MBB, DebugLoc(), TII.get(AMDGPU::S_BRANCH)).addMBB(entry.succ_MBB);
+ BuildMI(mezzanine_MBB, DebugLoc(), TII.get(AMDGPU::S_BRANCH))
+ .addMBB(entry.succ_MBB);
mezzanine_MBB->addSuccessor(entry.succ_MBB);
// Move instructions to mezzanine block.
move_body(entry.body, *mezzanine_MBB);
for (MachineBasicBlock *pred_MBB : entry.pred_MBBs) {
- //Deal with predecessor to mezzanine succession.
+ // Deal with predecessor to mezzanine succession.
MachineInstr &branch_ins =
get_branch_with_dest(*pred_MBB, *entry.succ_MBB);
assert(branch_ins.getOperand(0).isMBB() && "Branch instruction isn't.");
@@ -208,15 +209,12 @@ static inline void normalize_ir_post_phi_elimination(MachineFunction &MF) {
}
namespace std {
- template <>
- struct hash<Register>
- {
- std::size_t operator()(const Register& r) const
- {
- return hash<unsigned>()(r);
- }
- };
-}
+template <> struct hash<Register> {
+ std::size_t operator()(const Register &r) const {
+ return hash<unsigned>()(r);
+ }
+};
+} // namespace std
static inline void hoist_unrelated_copies(MachineFunction &MF) {
for (MachineBasicBlock &MBB : MF)
@@ -234,15 +232,17 @@ static inline void hoist_unrelated_copies(MachineFunction &MF) {
}
while (!copy_move_it.isEnd()) {
- Epilog_Iterator next = copy_move_it; ++next;
+ Epilog_Iterator next = copy_move_it;
+ ++next;
if (copy_move_it->getOpcode() == AMDGPU::COPY &&
- !related_copy_sources.count(copy_move_it->getOperand(1).getReg())
- || copy_move_it->getOpcode() == AMDGPU::IMPLICIT_DEF) {
+ !related_copy_sources.count(
+ copy_move_it->getOperand(1).getReg()) ||
+ copy_move_it->getOpcode() == AMDGPU::IMPLICIT_DEF) {
MachineInstr &MI_to_move = *copy_move_it;
MI_to_move.removeFromBundle();
- MBB.insert(branch_MI.getIterator(),&MI_to_move);
+ MBB.insert(branch_MI.getIterator(), &MI_to_move);
}
-
+
copy_move_it = next;
}
}
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
index c6b8ace9d..61cef630e 100644
--- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -48,12 +48,12 @@
/// %exec = S_OR_B64 %exec, %sgpr0 // Re-enable saved exec mask bits
//===----------------------------------------------------------------------===//
-#include "SICustomBranchBundles.h"
#include "SILowerControlFlow.h"
#include "AMDGPU.h"
#include "AMDGPULaneMaskUtils.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
+#include "SICustomBranchBundles.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveVariables.h"
@@ -160,7 +160,7 @@ public:
MachineFunctionProperties getClearedProperties() const override {
return MachineFunctionProperties().setNoPHIs();
}
-
+
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addUsedIfAvailable<LiveIntervalsWrapperPass>();
// Should preserve the same set that TwoAddressInstructions does.
diff --git a/llvm/lib/Target/AMDGPU/SIRestoreNormalEpilog.cpp b/llvm/lib/Target/AMDGPU/SIRestoreNormalEpilog.cpp
index ef565a9d9..a8fd70262 100644
--- a/llvm/lib/Target/AMDGPU/SIRestoreNormalEpilog.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRestoreNormalEpilog.cpp
@@ -1,7 +1,7 @@
-#include "SICustomBranchBundles.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
+#include "SICustomBranchBundles.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveVariables.h"
@@ -12,8 +12,7 @@
#define DEBUG_TYPE "si-restore-normal-epilog"
-namespace
-{
+namespace {
class SIRestoreNormalEpilogLegacy : public MachineFunctionPass {
public:
@@ -34,7 +33,6 @@ public:
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().setNoPHIs();
}
-
};
} // namespace
``````````
</details>
https://github.com/llvm/llvm-project/pull/159557
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