[llvm] d76d0a5 - [AArch64] Regenerate and update a number of check lines. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 18 01:54:52 PDT 2025
Author: David Green
Date: 2025-09-18T09:54:47+01:00
New Revision: d76d0a5139010068aceaedcd3683d9500800ee98
URL: https://github.com/llvm/llvm-project/commit/d76d0a5139010068aceaedcd3683d9500800ee98
DIFF: https://github.com/llvm/llvm-project/commit/d76d0a5139010068aceaedcd3683d9500800ee98.diff
LOG: [AArch64] Regenerate and update a number of check lines. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll
llvm/test/CodeGen/AArch64/aarch64-mulv.ll
llvm/test/CodeGen/AArch64/arm64-fp-contract-zero.ll
llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
llvm/test/CodeGen/AArch64/arm64-vadd.ll
llvm/test/CodeGen/AArch64/arm64-vmul.ll
llvm/test/CodeGen/AArch64/call-rv-marker.ll
llvm/test/CodeGen/AArch64/callbr-prepare.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll
llvm/test/CodeGen/AArch64/fnmul.ll
llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
llvm/test/CodeGen/AArch64/fp-intrinsics.ll
llvm/test/CodeGen/AArch64/freeze.ll
llvm/test/CodeGen/AArch64/ldexp-arm64ec.ll
llvm/test/CodeGen/AArch64/neon-addlv.ll
llvm/test/CodeGen/AArch64/ptrauth-fpac.ll
llvm/test/CodeGen/AArch64/remat-const-float-simd.ll
llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
llvm/test/CodeGen/AArch64/sme-avoid-coalescing-locally-streaming.ll
llvm/test/CodeGen/AArch64/sme-za-exceptions.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll
llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-dsp-undef.ll
llvm/test/CodeGen/AArch64/sve2p1-intrinsics-pmov-to-pred.ll
llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
llvm/test/CodeGen/AArch64/vector-lrint.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll b/llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll
index b07ba763d20ec..f900f0209a108 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll
@@ -35,8 +35,8 @@ define <8 x i16> @rhaddu_zext(<8 x i8> %a0, <8 x i8> %a1) {
define <8 x i16> @hadds_zext(<8 x i8> %a0, <8 x i8> %a1) {
; CHECK-LABEL: hadds_zext:
; CHECK: // %bb.0:
-; CHECK-NEXT: uhadd v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-NEXT: uhadd v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-NEXT: ret
%x0 = zext <8 x i8> %a0 to <8 x i16>
%x1 = zext <8 x i8> %a1 to <8 x i16>
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mulv.ll b/llvm/test/CodeGen/AArch64/aarch64-mulv.ll
index e11ae9a251590..fecc6554667fa 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mulv.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mulv.ll
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=aarch64 -aarch64-enable-sink-fold=true -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64 -aarch64-enable-sink-fold=true -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK_GI: warning: Instruction selection used fallback path for mulv_v3i64
+; CHECK-GI: warning: Instruction selection used fallback path for mulv_v3i32
declare i8 @llvm.vector.reduce.mul.v2i8(<2 x i8>)
declare i8 @llvm.vector.reduce.mul.v3i8(<3 x i8>)
diff --git a/llvm/test/CodeGen/AArch64/arm64-fp-contract-zero.ll b/llvm/test/CodeGen/AArch64/arm64-fp-contract-zero.ll
index 53e69b985cafb..acb7080838239 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fp-contract-zero.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fp-contract-zero.ll
@@ -7,7 +7,7 @@
define double @test_fms_fold(double %a, double %b) {
; CHECK-LABEL: test_fms_fold:
; CHECK: // %bb.0:
-; CHECK-NEXT: movi {{d[0-9]+}}, #0000000000000000
+; CHECK-NEXT: movi d0, #0000000000000000
; CHECK-NEXT: ret
%mul = fmul fast double %a, 0.000000e+00
%mul1 = fmul fast double %b, 0.000000e+00
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
index 367105f783817..e18a5f695ba29 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
@@ -4,6 +4,8 @@
; CHECK-GI: warning: Instruction selection used fallback path for test_bitcastv2f32tov1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_bitcastv1f64tov2f32
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_concat_v1i32_undef
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_concat_
diff _v1i32_v1i32
define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) {
; CHECK-LABEL: ins16bw:
diff --git a/llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll b/llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
index a6a825b26b3b5..84879d15de238 100644
--- a/llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
@@ -2,12 +2,12 @@
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; Test efficient codegen of vector extends up from legal type to 128 bit
-; and 256 bit vector types.
-
; CHECK-GI: warning: Instruction selection used fallback path for zext_v32i1
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for zext_v64i1
+; Test efficient codegen of vector extends up from legal type to 128 bit
+; and 256 bit vector types.
+
;-----
; Vectors of i16.
;-----
diff --git a/llvm/test/CodeGen/AArch64/arm64-vadd.ll b/llvm/test/CodeGen/AArch64/arm64-vadd.ll
index f9263185f308e..11fb73237da07 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vadd.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vadd.ll
@@ -2,8 +2,8 @@
; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=arm64-eabi -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-GI: warning: Instruction selection used fallback path for saddlp1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uaddlp1d
+; CHECK-GI: warning: Instruction selection used fallback path for saddlp1d
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uaddlp1d
define <8 x i8> @addhn8b(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: addhn8b:
diff --git a/llvm/test/CodeGen/AArch64/arm64-vmul.ll b/llvm/test/CodeGen/AArch64/arm64-vmul.ll
index d12f7ce33e246..e6df9f2fb2c56 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vmul.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vmul.ll
@@ -39,6 +39,7 @@
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqdmlsl_d
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_pmull_64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_pmull_high_64
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_commutable_pmull_64
define <8 x i16> @smull8h(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: smull8h:
diff --git a/llvm/test/CodeGen/AArch64/call-rv-marker.ll b/llvm/test/CodeGen/AArch64/call-rv-marker.ll
index b22370a295749..0bc64498da324 100644
--- a/llvm/test/CodeGen/AArch64/call-rv-marker.ll
+++ b/llvm/test/CodeGen/AArch64/call-rv-marker.ll
@@ -139,16 +139,16 @@ define dso_local void @rv_marker_3() personality ptr @__gxx_personality_v0 {
; SELDAG-NEXT: mov x29, x29
; SELDAG-NEXT: bl _objc_retainAutoreleasedReturnValue
; SELDAG-NEXT: mov x19, x0
-; SELDAG-NEXT: Ltmp0:
+; SELDAG-NEXT: Ltmp0: ; EH_LABEL
; SELDAG-NEXT: bl _objc_object
-; SELDAG-NEXT: Ltmp1:
+; SELDAG-NEXT: Ltmp1: ; EH_LABEL
; SELDAG-NEXT: ; %bb.1: ; %invoke.cont
; SELDAG-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; SELDAG-NEXT: mov x0, x19
; SELDAG-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
; SELDAG-NEXT: b _objc_release
; SELDAG-NEXT: LBB3_2: ; %lpad
-; SELDAG-NEXT: Ltmp2:
+; SELDAG-NEXT: Ltmp2: ; EH_LABEL
; SELDAG-NEXT: mov x20, x0
; SELDAG-NEXT: mov x0, x19
; SELDAG-NEXT: bl _objc_release
@@ -197,9 +197,9 @@ define dso_local void @rv_marker_3() personality ptr @__gxx_personality_v0 {
; GISEL-NEXT: mov x29, x29
; GISEL-NEXT: bl _objc_retainAutoreleasedReturnValue
; GISEL-NEXT: mov x19, x0
-; GISEL-NEXT: Ltmp0:
+; GISEL-NEXT: Ltmp0: ; EH_LABEL
; GISEL-NEXT: bl _objc_object
-; GISEL-NEXT: Ltmp1:
+; GISEL-NEXT: Ltmp1: ; EH_LABEL
; GISEL-NEXT: ; %bb.1: ; %invoke.cont
; GISEL-NEXT: Lloh0:
; GISEL-NEXT: adrp x1, _objc_release at GOTPAGE
@@ -210,7 +210,7 @@ define dso_local void @rv_marker_3() personality ptr @__gxx_personality_v0 {
; GISEL-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
; GISEL-NEXT: br x1
; GISEL-NEXT: LBB3_2: ; %lpad
-; GISEL-NEXT: Ltmp2:
+; GISEL-NEXT: Ltmp2: ; EH_LABEL
; GISEL-NEXT: Lloh2:
; GISEL-NEXT: adrp x8, _objc_release at GOTPAGE
; GISEL-NEXT: mov x20, x0
@@ -278,16 +278,16 @@ define dso_local void @rv_marker_4() personality ptr @__gxx_personality_v0 {
; SELDAG-NEXT: .cfi_offset w29, -16
; SELDAG-NEXT: .cfi_offset w19, -24
; SELDAG-NEXT: .cfi_offset w20, -32
-; SELDAG-NEXT: Ltmp3:
+; SELDAG-NEXT: Ltmp3: ; EH_LABEL
; SELDAG-NEXT: bl _foo1
; SELDAG-NEXT: mov x29, x29
; SELDAG-NEXT: bl _objc_retainAutoreleasedReturnValue
-; SELDAG-NEXT: Ltmp4:
+; SELDAG-NEXT: Ltmp4: ; EH_LABEL
; SELDAG-NEXT: ; %bb.1: ; %invoke.cont
-; SELDAG-NEXT: Ltmp6:
+; SELDAG-NEXT: Ltmp6: ; EH_LABEL
; SELDAG-NEXT: mov x19, x0
; SELDAG-NEXT: bl _objc_object
-; SELDAG-NEXT: Ltmp7:
+; SELDAG-NEXT: Ltmp7: ; EH_LABEL
; SELDAG-NEXT: ; %bb.2: ; %invoke.cont2
; SELDAG-NEXT: mov x0, x19
; SELDAG-NEXT: bl _objc_release
@@ -298,13 +298,13 @@ define dso_local void @rv_marker_4() personality ptr @__gxx_personality_v0 {
; SELDAG-NEXT: add sp, sp, #48
; SELDAG-NEXT: ret
; SELDAG-NEXT: LBB4_3: ; %lpad1
-; SELDAG-NEXT: Ltmp8:
+; SELDAG-NEXT: Ltmp8: ; EH_LABEL
; SELDAG-NEXT: mov x20, x0
; SELDAG-NEXT: mov x0, x19
; SELDAG-NEXT: bl _objc_release
; SELDAG-NEXT: b LBB4_5
; SELDAG-NEXT: LBB4_4: ; %lpad
-; SELDAG-NEXT: Ltmp5:
+; SELDAG-NEXT: Ltmp5: ; EH_LABEL
; SELDAG-NEXT: mov x20, x0
; SELDAG-NEXT: LBB4_5: ; %ehcleanup
; SELDAG-NEXT: add x0, sp, #15
@@ -351,16 +351,16 @@ define dso_local void @rv_marker_4() personality ptr @__gxx_personality_v0 {
; GISEL-NEXT: .cfi_offset w29, -16
; GISEL-NEXT: .cfi_offset w19, -24
; GISEL-NEXT: .cfi_offset w20, -32
-; GISEL-NEXT: Ltmp3:
+; GISEL-NEXT: Ltmp3: ; EH_LABEL
; GISEL-NEXT: bl _foo1
; GISEL-NEXT: mov x29, x29
; GISEL-NEXT: bl _objc_retainAutoreleasedReturnValue
-; GISEL-NEXT: Ltmp4:
+; GISEL-NEXT: Ltmp4: ; EH_LABEL
; GISEL-NEXT: ; %bb.1: ; %invoke.cont
-; GISEL-NEXT: Ltmp6:
+; GISEL-NEXT: Ltmp6: ; EH_LABEL
; GISEL-NEXT: mov x19, x0
; GISEL-NEXT: bl _objc_object
-; GISEL-NEXT: Ltmp7:
+; GISEL-NEXT: Ltmp7: ; EH_LABEL
; GISEL-NEXT: ; %bb.2: ; %invoke.cont2
; GISEL-NEXT: Lloh4:
; GISEL-NEXT: adrp x8, _objc_release at GOTPAGE
@@ -375,7 +375,7 @@ define dso_local void @rv_marker_4() personality ptr @__gxx_personality_v0 {
; GISEL-NEXT: add sp, sp, #48
; GISEL-NEXT: ret
; GISEL-NEXT: LBB4_3: ; %lpad1
-; GISEL-NEXT: Ltmp8:
+; GISEL-NEXT: Ltmp8: ; EH_LABEL
; GISEL-NEXT: Lloh6:
; GISEL-NEXT: adrp x8, _objc_release at GOTPAGE
; GISEL-NEXT: mov x20, x0
@@ -385,7 +385,7 @@ define dso_local void @rv_marker_4() personality ptr @__gxx_personality_v0 {
; GISEL-NEXT: blr x8
; GISEL-NEXT: b LBB4_5
; GISEL-NEXT: LBB4_4: ; %lpad
-; GISEL-NEXT: Ltmp5:
+; GISEL-NEXT: Ltmp5: ; EH_LABEL
; GISEL-NEXT: mov x20, x0
; GISEL-NEXT: LBB4_5: ; %ehcleanup
; GISEL-NEXT: add x0, sp, #15
diff --git a/llvm/test/CodeGen/AArch64/callbr-prepare.ll b/llvm/test/CodeGen/AArch64/callbr-prepare.ll
index afe18ca8b7c50..826e27d92720f 100644
--- a/llvm/test/CodeGen/AArch64/callbr-prepare.ll
+++ b/llvm/test/CodeGen/AArch64/callbr-prepare.ll
@@ -6,13 +6,13 @@ define i32 @test0() {
; CHECK-LABEL: @test0(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[OUT:%.*]] = callbr i32 asm "# $0", "=r,!i"()
-; CHECK-NEXT: to label [[DIRECT:%.*]] [label %entry.indirect_crit_edge]
+; CHECK-NEXT: to label [[DIRECT:%.*]] [label %entry.indirect_crit_edge]
; CHECK: entry.indirect_crit_edge:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[OUT]])
; CHECK-NEXT: br label [[INDIRECT:%.*]]
; CHECK: direct:
; CHECK-NEXT: [[OUT2:%.*]] = callbr i32 asm "# $0", "=r,!i"()
-; CHECK-NEXT: to label [[DIRECT2:%.*]] [label %direct.indirect_crit_edge]
+; CHECK-NEXT: to label [[DIRECT2:%.*]] [label %direct.indirect_crit_edge]
; CHECK: direct.indirect_crit_edge:
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[OUT2]])
; CHECK-NEXT: br label [[INDIRECT]]
@@ -42,7 +42,7 @@ define i32 @dont_split0() {
; CHECK-LABEL: @dont_split0(
; CHECK-NEXT: entry:
; CHECK-NEXT: callbr void asm "", "!i"()
-; CHECK-NEXT: to label [[X:%.*]] [label %y]
+; CHECK-NEXT: to label [[X:%.*]] [label %y]
; CHECK: x:
; CHECK-NEXT: ret i32 42
; CHECK: y:
@@ -68,7 +68,7 @@ define i32 @dont_split1() {
; CHECK-LABEL: @dont_split1(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT: to label [[X:%.*]] [label %y]
+; CHECK-NEXT: to label [[X:%.*]] [label %y]
; CHECK: x:
; CHECK-NEXT: ret i32 42
; CHECK: y:
@@ -93,7 +93,7 @@ define i32 @dont_split2() {
; CHECK-LABEL: @dont_split2(
; CHECK-NEXT: entry:
; CHECK-NEXT: callbr void asm "", "!i"()
-; CHECK-NEXT: to label [[X:%.*]] [label %y]
+; CHECK-NEXT: to label [[X:%.*]] [label %y]
; CHECK: x:
; CHECK-NEXT: br label [[Y:%.*]]
; CHECK: y:
@@ -119,7 +119,7 @@ define i32 @dont_split3() {
; CHECK-LABEL: @dont_split3(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT: to label [[X:%.*]] [label %v]
+; CHECK-NEXT: to label [[X:%.*]] [label %v]
; CHECK: x:
; CHECK-NEXT: br label [[V:%.*]]
; CHECK: v:
@@ -142,7 +142,7 @@ define i32 @split_me0() {
; CHECK-LABEL: @split_me0(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT: to label [[X:%.*]] [label %entry.y_crit_edge]
+; CHECK-NEXT: to label [[X:%.*]] [label %entry.y_crit_edge]
; CHECK: entry.y_crit_edge:
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
; CHECK-NEXT: br label [[Y:%.*]]
@@ -173,7 +173,7 @@ define i32 @split_me1(i1 %z) {
; CHECK-NEXT: br i1 [[Z:%.*]], label [[W:%.*]], label [[V:%.*]]
; CHECK: w:
; CHECK-NEXT: [[TMP0:%.*]] = callbr i32 asm "", "=r,!i,!i"()
-; CHECK-NEXT: to label [[X:%.*]] [label [[W_V_CRIT_EDGE:%.*]], label %w.v_crit_edge]
+; CHECK-NEXT: to label [[X:%.*]] [label [[W_V_CRIT_EDGE:%.*]], label %w.v_crit_edge]
; CHECK: w.v_crit_edge:
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
; CHECK-NEXT: br label [[V]]
@@ -206,7 +206,7 @@ define i32 @split_me2(i1 %z) {
; CHECK-NEXT: br i1 [[Z:%.*]], label [[W:%.*]], label [[V:%.*]]
; CHECK: w:
; CHECK-NEXT: [[TMP0:%.*]] = callbr i32 asm "", "=r,!i,!i"()
-; CHECK-NEXT: to label [[X:%.*]] [label [[W_V_CRIT_EDGE:%.*]], label %w.v_crit_edge]
+; CHECK-NEXT: to label [[X:%.*]] [label [[W_V_CRIT_EDGE:%.*]], label %w.v_crit_edge]
; CHECK: w.v_crit_edge:
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
; CHECK-NEXT: br label [[V]]
@@ -236,7 +236,7 @@ define i32 @dont_split4() {
; CHECK-LABEL: @dont_split4(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT: to label [[X:%.*]] [label %y]
+; CHECK-NEXT: to label [[X:%.*]] [label %y]
; CHECK: x:
; CHECK-NEXT: br label [[OUT:%.*]]
; CHECK: y:
@@ -265,7 +265,7 @@ define i32 @dont_split5() {
; CHECK-LABEL: @dont_split5(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT: to label [[OUT:%.*]] [label %y]
+; CHECK-NEXT: to label [[OUT:%.*]] [label %y]
; CHECK: y:
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
; CHECK-NEXT: br label [[OUT]]
@@ -289,7 +289,7 @@ define i32 @split_me3() {
; CHECK-LABEL: @split_me3(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT: to label [[Y:%.*]] [label %entry.out_crit_edge]
+; CHECK-NEXT: to label [[Y:%.*]] [label %entry.out_crit_edge]
; CHECK: entry.out_crit_edge:
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
; CHECK-NEXT: br label [[OUT:%.*]]
@@ -318,7 +318,7 @@ define i32 @dont_split6(i32 %0) {
; CHECK: loop:
; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ [[TMP0:%.*]], [[ENTRY:%.*]] ], [ [[TMP3:%.*]], [[LOOP_LOOP_CRIT_EDGE:%.*]] ]
; CHECK-NEXT: [[TMP2:%.*]] = callbr i32 asm "", "=r,0,!i"(i32 [[TMP1]])
-; CHECK-NEXT: to label [[EXIT:%.*]] [label %loop.loop_crit_edge]
+; CHECK-NEXT: to label [[EXIT:%.*]] [label %loop.loop_crit_edge]
; CHECK: loop.loop_crit_edge:
; CHECK-NEXT: [[TMP3]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP2]])
; CHECK-NEXT: br label [[LOOP]]
@@ -339,7 +339,7 @@ define i32 @split_me4() {
; CHECK-LABEL: @split_me4(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT: to label [[SAME:%.*]] [label %entry.same_crit_edge]
+; CHECK-NEXT: to label [[SAME:%.*]] [label %entry.same_crit_edge]
; CHECK: entry.same_crit_edge:
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
; CHECK-NEXT: br label [[SAME]]
@@ -358,7 +358,7 @@ define i32 @split_me5() {
; CHECK-LABEL: @split_me5(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT: to label [[SAME:%.*]] [label %entry.same_crit_edge]
+; CHECK-NEXT: to label [[SAME:%.*]] [label %entry.same_crit_edge]
; CHECK: entry.same_crit_edge:
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
; CHECK-NEXT: br label [[SAME]]
@@ -379,13 +379,13 @@ define i64 @split_me6() {
; CHECK-LABEL: @split_me6(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = callbr i64 asm "# $0 $1", "={dx},!i"()
-; CHECK-NEXT: to label [[ASM_FALLTHROUGH:%.*]] [label %entry.foo_crit_edge]
+; CHECK-NEXT: to label [[ASM_FALLTHROUGH:%.*]] [label %entry.foo_crit_edge]
; CHECK: entry.foo_crit_edge:
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.callbr.landingpad.i64(i64 [[TMP0]])
; CHECK-NEXT: br label [[FOO:%.*]]
; CHECK: asm.fallthrough:
; CHECK-NEXT: [[TMP2:%.*]] = callbr i64 asm "# $0 $1", "={bx},!i"()
-; CHECK-NEXT: to label [[FOO]] [label %asm.fallthrough.foo_crit_edge]
+; CHECK-NEXT: to label [[FOO]] [label %asm.fallthrough.foo_crit_edge]
; CHECK: asm.fallthrough.foo_crit_edge:
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.callbr.landingpad.i64(i64 [[TMP2]])
; CHECK-NEXT: br label [[FOO]]
@@ -412,7 +412,7 @@ define i32 @multiple_split() {
; CHECK-LABEL: @multiple_split(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT: to label [[X:%.*]] [label %y]
+; CHECK-NEXT: to label [[X:%.*]] [label %y]
; CHECK: x:
; CHECK-NEXT: ret i32 42
; CHECK: y:
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll
index a5c64c0982d0f..bb043ecb5ecb3 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll
@@ -1,16 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16,+sve -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16,+sve2 -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc < %s --global-isel --global-isel-abort=2 --mattr=+complxnum,+neon,+fullfp16 -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; RUN: llc < %s --global-isel --global-isel-abort=2 --mattr=+complxnum,+neon,+fullfp16,+sve -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; RUN: llc < %s --global-isel --global-isel-abort=2 --mattr=+complxnum,+neon,+fullfp16,+sve2 -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-
-target triple = "aarch64"
-
-; CHECK-GI: warning: Instruction selection used fallback path for complex_add_v16f16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for complex_add_v32f16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for complex_add_v16f16_with_intrinsic
+; RUN: llc < %s -mtriple=aarch64 --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 --mattr=+complxnum,+neon,+fullfp16,+sve -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 --mattr=+complxnum,+neon,+fullfp16,+sve2 -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 --global-isel --global-isel-abort=2 --mattr=+complxnum,+neon,+fullfp16 -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc < %s -mtriple=aarch64 --global-isel --global-isel-abort=2 --mattr=+complxnum,+neon,+fullfp16,+sve -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc < %s -mtriple=aarch64 --global-isel --global-isel-abort=2 --mattr=+complxnum,+neon,+fullfp16,+sve2 -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for complex_add_v16f16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for complex_add_v32f16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for complex_add_v16f16_with_intrinsic
; Expected to not transform
define <2 x half> @complex_add_v2f16(<2 x half> %a, <2 x half> %b) {
diff --git a/llvm/test/CodeGen/AArch64/fnmul.ll b/llvm/test/CodeGen/AArch64/fnmul.ll
index 679287879a16d..0b145a282ba6a 100644
--- a/llvm/test/CodeGen/AArch64/fnmul.ll
+++ b/llvm/test/CodeGen/AArch64/fnmul.ll
@@ -8,7 +8,6 @@ define half @fnmul16(half noundef %x, half noundef %y) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fnmul h0, h0, h1
; CHECK-NEXT: ret
-;
entry:
%fneg = fneg fast half %x
%mul = fmul fast half %fneg, %y
@@ -20,7 +19,6 @@ define float @fnmul32(float noundef %x, float noundef %y) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fnmul s0, s0, s1
; CHECK-NEXT: ret
-;
entry:
%fneg = fneg float %x
%mul = fmul float %fneg, %y
@@ -32,7 +30,6 @@ define double @fnmul64(double noundef %x, double noundef %y) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fnmul d0, d0, d1
; CHECK-NEXT: ret
-;
entry:
%fneg = fneg fast double %x
%mul = fmul fast double %fneg, %y
@@ -44,7 +41,6 @@ define half @fnmul16_2(half noundef %x, half noundef %y) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fnmul h0, h1, h0
; CHECK-NEXT: ret
-;
entry:
%fneg = fneg fast half %y
%mul = fmul fast half %x, %fneg
@@ -56,7 +52,6 @@ define float @fnmul32_2(float noundef %x, float noundef %y) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fnmul s0, s1, s0
; CHECK-NEXT: ret
-;
entry:
%fneg = fneg fast float %y
%mul = fmul fast float %x, %fneg
@@ -68,7 +63,6 @@ define double @fnmul64_2(double noundef %x, double noundef %y) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fnmul d0, d1, d0
; CHECK-NEXT: ret
-;
entry:
%fneg = fneg double %y
%mul = fmul double %x, %fneg
diff --git a/llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll b/llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
index d323a7e677b5a..86029a7169abb 100644
--- a/llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
+++ b/llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
@@ -4,8 +4,6 @@
; RUN: llc -mtriple=aarch64 -global-isel=true -global-isel-abort=2 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc -mtriple=aarch64 -global-isel=true -global-isel-abort=2 -mattr=+fullfp16 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; Check that constrained fp intrinsics are correctly lowered.
-
; CHECK-GI: warning: Instruction selection used fallback path for add_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sub_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for mul_f16
@@ -81,6 +79,8 @@
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptrunc_f16_f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fpext_f32_f16
+; Check that constrained fp intrinsics are correctly lowered.
+
; Half-precision intrinsics
define half @add_f16(half %x, half %y) #0 {
diff --git a/llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll b/llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
index 1364c47adff2d..c3da22757f1d2 100644
--- a/llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
@@ -2,8 +2,6 @@
; RUN: llc -mtriple=aarch64 %s -disable-strictnode-mutation -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64 -global-isel=true -global-isel-abort=2 -disable-strictnode-mutation %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; Check that constrained fp vector intrinsics are correctly lowered.
-
; CHECK-GI: warning: Instruction selection used fallback path for add_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sub_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for mul_v4f32
@@ -82,6 +80,8 @@
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptrunc_v2f32_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fpext_v2f64_v2f32
+; Check that constrained fp vector intrinsics are correctly lowered.
+
; Single-precision intrinsics
define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) #0 {
diff --git a/llvm/test/CodeGen/AArch64/fp-intrinsics.ll b/llvm/test/CodeGen/AArch64/fp-intrinsics.ll
index 919585a9826b9..6f5719c8443d9 100644
--- a/llvm/test/CodeGen/AArch64/fp-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/fp-intrinsics.ll
@@ -2,8 +2,6 @@
; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64 -global-isel=true -global-isel-abort=2 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; Check that constrained fp intrinsics are correctly lowered.
-
; CHECK-GI: warning: Instruction selection used fallback path for add_f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sub_f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for mul_f32
@@ -243,6 +241,7 @@
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for exp_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for exp2_v1f64
+; Check that constrained fp intrinsics are correctly lowered.
; Single-precision intrinsics
diff --git a/llvm/test/CodeGen/AArch64/freeze.ll b/llvm/test/CodeGen/AArch64/freeze.ll
index 7a9d6b7e52457..fae3bbe2dcfba 100644
--- a/llvm/test/CodeGen/AArch64/freeze.ll
+++ b/llvm/test/CodeGen/AArch64/freeze.ll
@@ -3,6 +3,10 @@
; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel -global-isel-abort=2 2>&1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; CHECK-GI: warning: Instruction selection used fallback path for freeze_v2i8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_uhadd
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_urhadd
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_shadd
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_srhadd
%struct.T = type { i32, i32 }
diff --git a/llvm/test/CodeGen/AArch64/ldexp-arm64ec.ll b/llvm/test/CodeGen/AArch64/ldexp-arm64ec.ll
index 0fde7b95f5462..73e24bba98af2 100644
--- a/llvm/test/CodeGen/AArch64/ldexp-arm64ec.ll
+++ b/llvm/test/CodeGen/AArch64/ldexp-arm64ec.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=arm64ec-windows-msvc < %s | FileCheck -check-prefixes=ARM64EC %s
; Separate from ldexp.ll test because this errors on half cases
diff --git a/llvm/test/CodeGen/AArch64/neon-addlv.ll b/llvm/test/CodeGen/AArch64/neon-addlv.ll
index 50f555b18ff07..a747ee661adcd 100644
--- a/llvm/test/CodeGen/AArch64/neon-addlv.ll
+++ b/llvm/test/CodeGen/AArch64/neon-addlv.ll
@@ -2,7 +2,7 @@
; RUN: llc -mtriple aarch64-none-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple aarch64-none-linux-gnu -global-isel -global-isel-abort=2 2>&1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-GI: warning: Instruction selection used fallback path for uaddlv_v8i8_urshr
+; CHECK-GI: warning: Instruction selection used fallback path for uaddlv_v8i8_urshr
declare <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8>) nounwind readnone
declare <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8>) nounwind readnone
diff --git a/llvm/test/CodeGen/AArch64/ptrauth-fpac.ll b/llvm/test/CodeGen/AArch64/ptrauth-fpac.ll
index 8b5c07f54dc1d..787b8886c917b 100644
--- a/llvm/test/CodeGen/AArch64/ptrauth-fpac.ll
+++ b/llvm/test/CodeGen/AArch64/ptrauth-fpac.ll
@@ -7,97 +7,129 @@
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define i64 @test_auth_ia(i64 %arg, i64 %arg1) {
-; ALL-LABEL: test_auth_ia:
-; ALL: %bb.0:
-; DARWIN-NEXT: mov x16, x0
-; DARWIN-NEXT: autia x16, x1
-; DARWIN-NEXT: mov x0, x16
+; DARWIN-LABEL: test_auth_ia:
+; DARWIN: ; %bb.0:
+; DARWIN-NEXT: mov x16, x0
+; DARWIN-NEXT: autia x16, x1
+; DARWIN-NEXT: mov x0, x16
+; DARWIN-NEXT: ret
+;
+; ELF-LABEL: test_auth_ia:
+; ELF: // %bb.0:
; ELF-NEXT: autia x0, x1
-; ALL-NEXT: ret
+; ELF-NEXT: ret
%tmp = call i64 @llvm.ptrauth.auth(i64 %arg, i32 0, i64 %arg1)
ret i64 %tmp
}
define i64 @test_auth_ia_zero(i64 %arg) {
-; ALL-LABEL: test_auth_ia_zero:
-; ALL: %bb.0:
-; DARWIN-NEXT: mov x16, x0
-; DARWIN-NEXT: autiza x16
-; DARWIN-NEXT: mov x0, x16
+; DARWIN-LABEL: test_auth_ia_zero:
+; DARWIN: ; %bb.0:
+; DARWIN-NEXT: mov x16, x0
+; DARWIN-NEXT: autiza x16
+; DARWIN-NEXT: mov x0, x16
+; DARWIN-NEXT: ret
+;
+; ELF-LABEL: test_auth_ia_zero:
+; ELF: // %bb.0:
; ELF-NEXT: autiza x0
-; ALL-NEXT: ret
+; ELF-NEXT: ret
%tmp = call i64 @llvm.ptrauth.auth(i64 %arg, i32 0, i64 0)
ret i64 %tmp
}
define i64 @test_auth_ib(i64 %arg, i64 %arg1) {
-; ALL-LABEL: test_auth_ib:
-; ALL: %bb.0:
-; DARWIN-NEXT: mov x16, x0
-; DARWIN-NEXT: autib x16, x1
-; DARWIN-NEXT: mov x0, x16
+; DARWIN-LABEL: test_auth_ib:
+; DARWIN: ; %bb.0:
+; DARWIN-NEXT: mov x16, x0
+; DARWIN-NEXT: autib x16, x1
+; DARWIN-NEXT: mov x0, x16
+; DARWIN-NEXT: ret
+;
+; ELF-LABEL: test_auth_ib:
+; ELF: // %bb.0:
; ELF-NEXT: autib x0, x1
-; ALL-NEXT: ret
+; ELF-NEXT: ret
%tmp = call i64 @llvm.ptrauth.auth(i64 %arg, i32 1, i64 %arg1)
ret i64 %tmp
}
define i64 @test_auth_ib_zero(i64 %arg) {
-; ALL-LABEL: test_auth_ib_zero:
-; ALL: %bb.0:
-; DARWIN-NEXT: mov x16, x0
-; DARWIN-NEXT: autizb x16
-; DARWIN-NEXT: mov x0, x16
+; DARWIN-LABEL: test_auth_ib_zero:
+; DARWIN: ; %bb.0:
+; DARWIN-NEXT: mov x16, x0
+; DARWIN-NEXT: autizb x16
+; DARWIN-NEXT: mov x0, x16
+; DARWIN-NEXT: ret
+;
+; ELF-LABEL: test_auth_ib_zero:
+; ELF: // %bb.0:
; ELF-NEXT: autizb x0
-; ALL-NEXT: ret
+; ELF-NEXT: ret
%tmp = call i64 @llvm.ptrauth.auth(i64 %arg, i32 1, i64 0)
ret i64 %tmp
}
define i64 @test_auth_da(i64 %arg, i64 %arg1) {
-; ALL-LABEL: test_auth_da:
-; ALL: %bb.0:
-; DARWIN-NEXT: mov x16, x0
-; DARWIN-NEXT: autda x16, x1
-; DARWIN-NEXT: mov x0, x16
+; DARWIN-LABEL: test_auth_da:
+; DARWIN: ; %bb.0:
+; DARWIN-NEXT: mov x16, x0
+; DARWIN-NEXT: autda x16, x1
+; DARWIN-NEXT: mov x0, x16
+; DARWIN-NEXT: ret
+;
+; ELF-LABEL: test_auth_da:
+; ELF: // %bb.0:
; ELF-NEXT: autda x0, x1
-; ALL-NEXT: ret
+; ELF-NEXT: ret
%tmp = call i64 @llvm.ptrauth.auth(i64 %arg, i32 2, i64 %arg1)
ret i64 %tmp
}
define i64 @test_auth_da_zero(i64 %arg) {
-; ALL-LABEL: test_auth_da_zero:
-; ALL: %bb.0:
-; DARWIN-NEXT: mov x16, x0
-; DARWIN-NEXT: autdza x16
-; DARWIN-NEXT: mov x0, x16
+; DARWIN-LABEL: test_auth_da_zero:
+; DARWIN: ; %bb.0:
+; DARWIN-NEXT: mov x16, x0
+; DARWIN-NEXT: autdza x16
+; DARWIN-NEXT: mov x0, x16
+; DARWIN-NEXT: ret
+;
+; ELF-LABEL: test_auth_da_zero:
+; ELF: // %bb.0:
; ELF-NEXT: autdza x0
-; ALL-NEXT: ret
+; ELF-NEXT: ret
%tmp = call i64 @llvm.ptrauth.auth(i64 %arg, i32 2, i64 0)
ret i64 %tmp
}
define i64 @test_auth_db(i64 %arg, i64 %arg1) {
-; ALL-LABEL: test_auth_db:
-; ALL: %bb.0:
-; DARWIN-NEXT: mov x16, x0
-; DARWIN-NEXT: autdb x16, x1
-; DARWIN-NEXT: mov x0, x16
+; DARWIN-LABEL: test_auth_db:
+; DARWIN: ; %bb.0:
+; DARWIN-NEXT: mov x16, x0
+; DARWIN-NEXT: autdb x16, x1
+; DARWIN-NEXT: mov x0, x16
+; DARWIN-NEXT: ret
+;
+; ELF-LABEL: test_auth_db:
+; ELF: // %bb.0:
; ELF-NEXT: autdb x0, x1
-; ALL-NEXT: ret
+; ELF-NEXT: ret
%tmp = call i64 @llvm.ptrauth.auth(i64 %arg, i32 3, i64 %arg1)
ret i64 %tmp
}
define i64 @test_auth_db_zero(i64 %arg) {
-; ALL-LABEL: test_auth_db_zero:
-; ALL: %bb.0:
-; DARWIN-NEXT: mov x16, x0
-; DARWIN-NEXT: autdzb x16
-; DARWIN-NEXT: mov x0, x16
+; DARWIN-LABEL: test_auth_db_zero:
+; DARWIN: ; %bb.0:
+; DARWIN-NEXT: mov x16, x0
+; DARWIN-NEXT: autdzb x16
+; DARWIN-NEXT: mov x0, x16
+; DARWIN-NEXT: ret
+;
+; ELF-LABEL: test_auth_db_zero:
+; ELF: // %bb.0:
; ELF-NEXT: autdzb x0
-; ALL-NEXT: ret
+; ELF-NEXT: ret
%tmp = call i64 @llvm.ptrauth.auth(i64 %arg, i32 3, i64 0)
ret i64 %tmp
}
diff --git a/llvm/test/CodeGen/AArch64/remat-const-float-simd.ll b/llvm/test/CodeGen/AArch64/remat-const-float-simd.ll
index cdb8b86fc398f..2a19d258f1adf 100644
--- a/llvm/test/CodeGen/AArch64/remat-const-float-simd.ll
+++ b/llvm/test/CodeGen/AArch64/remat-const-float-simd.ll
@@ -7,27 +7,38 @@ target triple = "aarch64-unknown-linux-gnu"
; float foo(void) { return float(2147483648); }
define float @foo() {
-; CHECK-LABEL: foo:
-; CHECK: // %bb.0: // %entry
+; CHECK-NEON-LABEL: foo:
+; CHECK-NEON: // %bb.0: // %entry
; CHECK-NEON-NEXT: movi v0.2s, #79, lsl #24
-; CHECK-SCALAR-NEXT: mov w8, #1325400064
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SCALAR-LABEL: foo:
+; CHECK-SCALAR: // %bb.0: // %entry
+; CHECK-SCALAR-NEXT: mov w8, #1325400064 // =0x4f000000
; CHECK-SCALAR-NEXT: fmov s0, w8
-; CHECK-NEXT: ret
+; CHECK-SCALAR-NEXT: ret
entry:
ret float 0x41E0000000000000
}
; float foo2(float p) { return p + float(2147483648); }
define float @foo2(float %f) {
-; CHECK-LABEL: foo2:
-; CHECK: // %bb.0: // %entry
+; CHECK-NEON-LABEL: foo2:
+; CHECK-NEON: // %bb.0: // %entry
; CHECK-NEON-NEXT: movi v1.2s, #79, lsl #24
; CHECK-NEON-NEXT: fadd s0, s0, s1
-; CHECK-SCALAR-NEXT: mov w8, #1325400064
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SCALAR-LABEL: foo2:
+; CHECK-SCALAR: // %bb.0: // %entry
+; CHECK-SCALAR-NEXT: mov w8, #1325400064 // =0x4f000000
; CHECK-SCALAR-NEXT: fmov s1, w8
; CHECK-SCALAR-NEXT: fadd s0, s0, s1
-; CHECK-NEXT: ret
+; CHECK-SCALAR-NEXT: ret
entry:
%p = fadd float %f, 0x41E0000000000000
ret float %p
}
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll b/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
index 0091469edde92..d533ca1159183 100644
--- a/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
+++ b/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
@@ -521,7 +521,7 @@ define i32 @leaf_sign_all_a_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r
define i32 @leaf_sign_all_b_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-return-address"="all" "sign-return-address-key"="b_key" "branch-target-enforcement" {
; COMPAT-LABEL: leaf_sign_all_b_key_bti:
; COMPAT: // %bb.0:
-; COMPAT-NEXT: .cfi_b_key_frame
+; COMPAT-NEXT: .cfi_b_key_frame
; COMPAT-NEXT: hint #34
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: .cfi_negate_ra_state_with_pc
@@ -563,9 +563,9 @@ define i32 @leaf_sign_all_b_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r
define i32 @leaf_sign_all_v83_b_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-return-address"="all" "target-features"="+v8.3a" "sign-return-address-key"="b_key" "branch-target-enforcement" {
; CHECK-LABEL: leaf_sign_all_v83_b_key_bti:
; CHECK: // %bb.0:
-; CHECK-NEXT: .cfi_b_key_frame
-; CHECK-NEXT: hint #34
-; CHECK-NEXT: hint #39
+; CHECK-NEXT: .cfi_b_key_frame
+; CHECK-NEXT: hint #34
+; CHECK-NEXT: hint #39
; CHECK-NEXT: .cfi_negate_ra_state_with_pc
; CHECK-NEXT: .Ltmp12:
; CHECK-NEXT: pacibsp
diff --git a/llvm/test/CodeGen/AArch64/sme-avoid-coalescing-locally-streaming.ll b/llvm/test/CodeGen/AArch64/sme-avoid-coalescing-locally-streaming.ll
index 8e3866fcec89a..ba13a89fd9c1a 100644
--- a/llvm/test/CodeGen/AArch64/sme-avoid-coalescing-locally-streaming.ll
+++ b/llvm/test/CodeGen/AArch64/sme-avoid-coalescing-locally-streaming.ll
@@ -11,14 +11,14 @@ define void @dont_coalesce_args(<2 x i64> %a) "aarch64_pstate_sm_body" nounwind
; CHECK-COALESCER-BARRIER-NEXT: {{ $}}
; CHECK-COALESCER-BARRIER-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-COALESCER-BARRIER-NEXT: [[COALESCER_BARRIER_FPR128_:%[0-9]+]]:fpr128 = COALESCER_BARRIER_FPR128 [[COPY]]
- ; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg
+ ; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
; CHECK-COALESCER-BARRIER-NEXT: [[DEF:%[0-9]+]]:zpr = IMPLICIT_DEF
; CHECK-COALESCER-BARRIER-NEXT: [[INSERT_SUBREG:%[0-9]+]]:zpr = INSERT_SUBREG [[DEF]], [[COALESCER_BARRIER_FPR128_]], %subreg.zsub
; CHECK-COALESCER-BARRIER-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-COALESCER-BARRIER-NEXT: $z0 = COPY [[INSERT_SUBREG]]
; CHECK-COALESCER-BARRIER-NEXT: BL @scalable_args, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $z0, implicit-def $sp
; CHECK-COALESCER-BARRIER-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg
+ ; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
; CHECK-COALESCER-BARRIER-NEXT: RET_ReallyLR
;
; CHECK-REGALLOC-LABEL: name: dont_coalesce_args
@@ -26,13 +26,13 @@ define void @dont_coalesce_args(<2 x i64> %a) "aarch64_pstate_sm_body" nounwind
; CHECK-REGALLOC-NEXT: liveins: $q0
; CHECK-REGALLOC-NEXT: {{ $}}
; CHECK-REGALLOC-NEXT: STRQui $q0, %stack.0, 0 :: (store (s128) into %stack.0)
- ; CHECK-REGALLOC-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg
+ ; CHECK-REGALLOC-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
; CHECK-REGALLOC-NEXT: renamable $q0 = LDRQui %stack.0, 0 :: (load (s128) from %stack.0)
; CHECK-REGALLOC-NEXT: renamable $q0 = KILL killed renamable $q0, implicit-def $z0
; CHECK-REGALLOC-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-REGALLOC-NEXT: BL @scalable_args, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $z0, implicit-def $sp
; CHECK-REGALLOC-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-REGALLOC-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg
+ ; CHECK-REGALLOC-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
; CHECK-REGALLOC-NEXT: RET_ReallyLR
%sa = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> poison, <2 x i64> %a, i64 0)
call void @scalable_args(<vscale x 2 x i64> %sa)
@@ -42,26 +42,26 @@ define void @dont_coalesce_args(<2 x i64> %a) "aarch64_pstate_sm_body" nounwind
define <2 x i64> @dont_coalesce_res() "aarch64_pstate_sm_body" nounwind {
; CHECK-COALESCER-BARRIER-LABEL: name: dont_coalesce_res
; CHECK-COALESCER-BARRIER: bb.0 (%ir-block.0):
- ; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg
+ ; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
; CHECK-COALESCER-BARRIER-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-COALESCER-BARRIER-NEXT: BL @scalable_res, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $z0
; CHECK-COALESCER-BARRIER-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-COALESCER-BARRIER-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
; CHECK-COALESCER-BARRIER-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY [[COPY]].zsub
; CHECK-COALESCER-BARRIER-NEXT: [[COALESCER_BARRIER_FPR128_:%[0-9]+]]:fpr128 = COALESCER_BARRIER_FPR128 [[COPY1]]
- ; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $q0, implicit $vg, implicit-def $vg
+ ; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $q0, implicit $vg, implicit-def $vg, implicit-def $fpmr
; CHECK-COALESCER-BARRIER-NEXT: $q0 = COPY [[COALESCER_BARRIER_FPR128_]]
; CHECK-COALESCER-BARRIER-NEXT: RET_ReallyLR implicit $q0
;
; CHECK-REGALLOC-LABEL: name: dont_coalesce_res
; CHECK-REGALLOC: bb.0 (%ir-block.0):
- ; CHECK-REGALLOC-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg
+ ; CHECK-REGALLOC-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
; CHECK-REGALLOC-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-REGALLOC-NEXT: BL @scalable_res, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $z0
; CHECK-REGALLOC-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-REGALLOC-NEXT: renamable $q0 = KILL renamable $q0, implicit killed $z0
; CHECK-REGALLOC-NEXT: STRQui killed renamable $q0, %stack.0, 0 :: (store (s128) into %stack.0)
- ; CHECK-REGALLOC-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def dead $q0, implicit $vg, implicit-def $vg
+ ; CHECK-REGALLOC-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def dead $q0, implicit $vg, implicit-def $vg, implicit-def $fpmr
; CHECK-REGALLOC-NEXT: $q0 = LDRQui %stack.0, 0 :: (load (s128) from %stack.0)
; CHECK-REGALLOC-NEXT: RET_ReallyLR implicit $q0
%sa = call <vscale x 2 x i64> @scalable_res()
@@ -76,7 +76,7 @@ define <2 x i64> @dont_coalesce_arg_that_is_also_res(<2 x i64> %a) "aarch64_psta
; CHECK-COALESCER-BARRIER-NEXT: {{ $}}
; CHECK-COALESCER-BARRIER-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-COALESCER-BARRIER-NEXT: [[COALESCER_BARRIER_FPR128_:%[0-9]+]]:fpr128 = COALESCER_BARRIER_FPR128 [[COPY]]
- ; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg
+ ; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
; CHECK-COALESCER-BARRIER-NEXT: [[DEF:%[0-9]+]]:zpr = IMPLICIT_DEF
; CHECK-COALESCER-BARRIER-NEXT: [[INSERT_SUBREG:%[0-9]+]]:zpr = INSERT_SUBREG [[DEF]], [[COALESCER_BARRIER_FPR128_]], %subreg.zsub
; CHECK-COALESCER-BARRIER-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
@@ -84,7 +84,7 @@ define <2 x i64> @dont_coalesce_arg_that_is_also_res(<2 x i64> %a) "aarch64_psta
; CHECK-COALESCER-BARRIER-NEXT: BL @scalable_args, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $z0, implicit-def $sp
; CHECK-COALESCER-BARRIER-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-COALESCER-BARRIER-NEXT: [[COALESCER_BARRIER_FPR128_1:%[0-9]+]]:fpr128 = COALESCER_BARRIER_FPR128 [[COALESCER_BARRIER_FPR128_]]
- ; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $q0, implicit $vg, implicit-def $vg
+ ; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $q0, implicit $vg, implicit-def $vg, implicit-def $fpmr
; CHECK-COALESCER-BARRIER-NEXT: $q0 = COPY [[COALESCER_BARRIER_FPR128_1]]
; CHECK-COALESCER-BARRIER-NEXT: RET_ReallyLR implicit $q0
;
@@ -93,13 +93,13 @@ define <2 x i64> @dont_coalesce_arg_that_is_also_res(<2 x i64> %a) "aarch64_psta
; CHECK-REGALLOC-NEXT: liveins: $q0
; CHECK-REGALLOC-NEXT: {{ $}}
; CHECK-REGALLOC-NEXT: STRQui $q0, %stack.0, 0 :: (store (s128) into %stack.0)
- ; CHECK-REGALLOC-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg
+ ; CHECK-REGALLOC-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
; CHECK-REGALLOC-NEXT: renamable $q0 = LDRQui %stack.0, 0 :: (load (s128) from %stack.0)
; CHECK-REGALLOC-NEXT: renamable $q0 = KILL killed renamable $q0, implicit-def $z0
; CHECK-REGALLOC-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-REGALLOC-NEXT: BL @scalable_args, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $z0, implicit-def $sp
; CHECK-REGALLOC-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-REGALLOC-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def dead $q0, implicit $vg, implicit-def $vg
+ ; CHECK-REGALLOC-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def dead $q0, implicit $vg, implicit-def $vg, implicit-def $fpmr
; CHECK-REGALLOC-NEXT: $q0 = LDRQui %stack.0, 0 :: (load (s128) from %stack.0)
; CHECK-REGALLOC-NEXT: RET_ReallyLR implicit $q0
%sa = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> poison, <2 x i64> %a, i64 0)
diff --git a/llvm/test/CodeGen/AArch64/sme-za-exceptions.ll b/llvm/test/CodeGen/AArch64/sme-za-exceptions.ll
index bb88142efa592..fc43c714d69b3 100644
--- a/llvm/test/CodeGen/AArch64/sme-za-exceptions.ll
+++ b/llvm/test/CodeGen/AArch64/sme-za-exceptions.ll
@@ -56,12 +56,12 @@ define void @za_with_raii(i1 %fail) "aarch64_inout_za" personality ptr @__gxx_pe
; CHECK-NEXT: adrp x8, .L.str
; CHECK-NEXT: add x8, x8, :lo12:.L.str
; CHECK-NEXT: str x8, [x0]
-; CHECK-NEXT: .Ltmp0:
+; CHECK-NEXT: .Ltmp0: // EH_LABEL
; CHECK-NEXT: adrp x1, :got:typeinfo_for_char_const_ptr
; CHECK-NEXT: mov x2, xzr
; CHECK-NEXT: ldr x1, [x1, :got_lo12:typeinfo_for_char_const_ptr]
; CHECK-NEXT: bl __cxa_throw
-; CHECK-NEXT: .Ltmp1:
+; CHECK-NEXT: .Ltmp1: // EH_LABEL
; CHECK-NEXT: smstart za
; CHECK-NEXT: mrs x8, TPIDR2_EL0
; CHECK-NEXT: sub x0, x29, #16
@@ -72,7 +72,7 @@ define void @za_with_raii(i1 %fail) "aarch64_inout_za" personality ptr @__gxx_pe
; CHECK-NEXT: msr TPIDR2_EL0, xzr
; CHECK-NEXT: // %bb.5: // %throw_fail
; CHECK-NEXT: .LBB0_6: // %unwind_dtors
-; CHECK-NEXT: .Ltmp2:
+; CHECK-NEXT: .Ltmp2: // EH_LABEL
; CHECK-NEXT: mov x19, x0
; CHECK-NEXT: smstart za
; CHECK-NEXT: mrs x8, TPIDR2_EL0
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll
index 4d4b1b67bbafc..3220de1007ab6 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll
@@ -60,7 +60,7 @@ define <vscale x 8 x i16> @index_ii_range_combine(i16 %a) {
; CHECK-NEXT: ret
%val2 = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 0, i16 2)
%val3 = shl <vscale x 8 x i16> %val2, splat(i16 2)
- %out = add <vscale x 8 x i16> %val3, splat(i16 2)
+ %out = add <vscale x 8 x i16> %val3, splat(i16 2)
ret <vscale x 8 x i16> %out
}
@@ -120,7 +120,7 @@ define <vscale x 4 x i32> @index_ir_range_combine(i32 %a) {
; CHECK-NEXT: index z0.s, #0, w0
; CHECK-NEXT: ret
%tmp = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 2, i32 1)
- %tmp1 = sub <vscale x 4 x i32> %tmp, splat(i32 2)
+ %tmp1 = sub <vscale x 4 x i32> %tmp, splat(i32 2)
%val2 = insertelement <vscale x 4 x i32> poison, i32 %a, i32 0
%val3 = shufflevector <vscale x 4 x i32> %val2, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%out = mul <vscale x 4 x i32> %tmp1, %val3
diff --git a/llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-dsp-undef.ll b/llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-dsp-undef.ll
index 15c3d48d907b1..13e1eae8caec8 100644
--- a/llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-dsp-undef.ll
+++ b/llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-dsp-undef.ll
@@ -105,4 +105,4 @@ declare <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.u.nxv2i64(<vscale x 2 x i1>,
declare <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
declare <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
declare <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
\ No newline at end of file
+declare <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
diff --git a/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-pmov-to-pred.ll b/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-pmov-to-pred.ll
index a6f6960507b71..aec5eedca0d0c 100644
--- a/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-pmov-to-pred.ll
+++ b/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-pmov-to-pred.ll
@@ -7,7 +7,7 @@
define <vscale x 16 x i1> @test_pmov_to_pred_i8(<vscale x 16 x i8> %zn) {
; CHECK-LABEL: test_pmov_to_pred_i8:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: pmov p0.b, z0
+; CHECK-NEXT: pmov p0.b, z0
; CHECK-NEXT: ret
entry:
%res = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8> %zn, i32 0)
@@ -17,10 +17,10 @@ define <vscale x 16 x i1> @test_pmov_to_pred_i8(<vscale x 16 x i8> %zn) {
define <vscale x 8 x i1> @test_pmov_to_pred_i16(<vscale x 8 x i16> %zn) {
; CHECK-LABEL: test_pmov_to_pred_i16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: pmov p1.h, z0[0]
-; CHECK-NEXT: pmov p2.h, z0[1]
-; CHECK-NEXT: eor p0.b, p0/z, p1.b, p2.b
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: pmov p1.h, z0[0]
+; CHECK-NEXT: pmov p2.h, z0[1]
+; CHECK-NEXT: eor p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT: ret
entry:
%res1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16> %zn, i32 0)
@@ -33,10 +33,10 @@ define <vscale x 8 x i1> @test_pmov_to_pred_i16(<vscale x 8 x i16> %zn) {
define <vscale x 4 x i1> @test_pmov_to_pred_i32(<vscale x 4 x i32> %zn) {
; CHECK-LABEL: test_pmov_to_pred_i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: pmov p1.s, z0[0]
-; CHECK-NEXT: pmov p2.s, z0[3]
-; CHECK-NEXT: eor p0.b, p0/z, p1.b, p2.b
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: pmov p1.s, z0[0]
+; CHECK-NEXT: pmov p2.s, z0[3]
+; CHECK-NEXT: eor p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT: ret
entry:
%res1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32> %zn, i32 0)
@@ -49,10 +49,10 @@ define <vscale x 4 x i1> @test_pmov_to_pred_i32(<vscale x 4 x i32> %zn) {
define <vscale x 2 x i1> @test_pmov_to_pred_i64(<vscale x 2 x i64> %zn) {
; CHECK-LABEL: test_pmov_to_pred_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: pmov p1.d, z0[0]
-; CHECK-NEXT: pmov p2.d, z0[7]
-; CHECK-NEXT: eor p0.b, p0/z, p1.b, p2.b
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: pmov p1.d, z0[0]
+; CHECK-NEXT: pmov p2.d, z0[7]
+; CHECK-NEXT: eor p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT: ret
entry:
%res1 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64> %zn, i32 0)
diff --git a/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll b/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
index 25702ef25510c..80029fb717575 100644
--- a/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
+++ b/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
@@ -2,16 +2,16 @@
; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon -aarch64-enable-collect-loh=false -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon -aarch64-enable-collect-loh=false -global-isel -global-isel-abort=2 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; Basic tests from input vector to bitmask
-; IR generated from clang for:
-; __builtin_convertvector + reinterpret_cast<uint16&>
-
; CHECK-GI: warning: Instruction selection used fallback path for convert_to_bitmask2
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for clang_builtins_undef_concat_convert_to_bitmask4
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for convert_to_bitmask_2xi32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for convert_to_bitmask_8xi2
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for no_direct_convert_for_bad_concat
+; Basic tests from input vector to bitmask
+; IR generated from clang for:
+; __builtin_convertvector + reinterpret_cast<uint16&>
+
define i16 @convert_to_bitmask16(<16 x i8> %vec) {
; Bits used in mask
; CHECK-SD-LABEL: convert_to_bitmask16:
diff --git a/llvm/test/CodeGen/AArch64/vector-lrint.ll b/llvm/test/CodeGen/AArch64/vector-lrint.ll
index 927c6142138b3..65839b21b5356 100644
--- a/llvm/test/CodeGen/AArch64/vector-lrint.ll
+++ b/llvm/test/CodeGen/AArch64/vector-lrint.ll
@@ -28,7 +28,12 @@
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f64
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16f64
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v32f64
-
+; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v1fp128
+; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v2fp128
+; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4fp128
+; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8fp128
+; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16fp128
+;
; CHECK-i64-GI: warning: Instruction selection used fallback path for lrint_v2f16
; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4f16
; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f16
@@ -44,6 +49,11 @@
; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f64
; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16f64
; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v32f64
+; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v2fp128
+; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4fp128
+; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8fp128
+; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16fp128
+
define <1 x iXLen> @lrint_v1f16(<1 x half> %x) nounwind {
; CHECK-i32-LABEL: lrint_v1f16:
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