[clang] [llvm] [RISCV] Add MVendorID, MArchID, and MImpID for sifive-p550. (PR #159465)

[Craig Topper via llvm-commits]

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/159465

>From 5450ee627726fe89312a9223ea27ff5251c86caf Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 17 Sep 2025 15:01:47 -0700
Subject: [PATCH 1/2] [RISCV] Add MVendorID, MArchID, and MImpID for
 sifive-p550.

cat /proc/cpuinfo from HiFive Premier board

processor	: 0
hart		: 0
isa		: rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf
mmu		: sv48
mvendorid	: 0x489
marchid		: 0x8000000000000008
mimpid		: 0x6220425
---
 llvm/lib/Target/RISCV/RISCVProcessors.td | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 36d63ed23b925..95f8a8789fa6c 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -390,7 +390,11 @@ def SIFIVE_P550 : RISCVProcessorModel<"sifive-p550", SiFiveP500Model,
                                        FeatureStdExtC,
                                        FeatureStdExtZba,
                                        FeatureStdExtZbb],
-                                      SiFiveP500TuneFeatures>;
+                                      SiFiveP500TuneFeatures> {
+  let MVendorID = 0x489;
+  let MArchID = 0x8000000000000008;
+  let MImpID = 0x6220425;
+}
 
 def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
                                       !listconcat(RVA22U64Features,

>From 945f30485e1a991c3b839e4e90c4fdf5186f8176 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 17 Sep 2025 21:05:44 -0700
Subject: [PATCH 2/2] fixup! add test

---
 clang/test/CodeGen/RISCV/builtin-cpu-is.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/clang/test/CodeGen/RISCV/builtin-cpu-is.c b/clang/test/CodeGen/RISCV/builtin-cpu-is.c
index 3cb3558a751ae..45007e512280e 100644
--- a/clang/test/CodeGen/RISCV/builtin-cpu-is.c
+++ b/clang/test/CodeGen/RISCV/builtin-cpu-is.c
@@ -37,3 +37,21 @@ int test_cpu_is_veyron_v1() {
 int test_cpu_is_spacemit_x60() {
   return __builtin_cpu_is("spacemit-x60");
 }
+
+// CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_sifive_p550(
+// CHECK-RV64-SAME: ) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  [[ENTRY:.*:]]
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1161
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 1), align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -9223372036854775800
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 2), align 8
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 102892581
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]
+// CHECK-RV64-NEXT:    [[CONV:%.*]] = zext i1 [[TMP7]] to i32
+// CHECK-RV64-NEXT:    ret i32 [[CONV]]
+//
+int test_cpu_is_sifive_p550() {
+  return __builtin_cpu_is("sifive-p550");
+}