[llvm] [TableGen][DecoderEmitter] Add extractBits() overloads (PR #159405)

[Craig Topper via llvm-commits]

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@@ -58,6 +59,24 @@ uint64_t fieldFromInstruction(const std::bitset<N> &Insn, unsigned StartBit,
   return ((Insn >> StartBit) & Mask).to_ullong();
 }
 
+template <unsigned StartBit, unsigned NumBits, typename T>
+inline std::enable_if_t<std::is_unsigned_v<T>, T> extractBits(T Val) {
+  static_assert(StartBit + NumBits <= std::numeric_limits<T>::digits);
+  return (Val >> StartBit) & maskTrailingOnes<T>(NumBits);
+}
+
+template <unsigned StartBit, unsigned NumBits, size_t N>
+uint64_t extractBits(const std::bitset<N> &Val) {
+  static_assert(StartBit + NumBits <= N);
+  std::bitset<N> Mask = maskTrailingOnes<uint64_t>(NumBits);
+  return ((Val >> StartBit) & Mask).to_ullong();
+}
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topperc wrote:

I thought RISC-V was using uint64_t for 48 bit instructions until 64 bit instructions are needed?

https://github.com/llvm/llvm-project/pull/159405