[llvm] [RegAlloc] Allow rematerialization with virtual reg uses (PR #159211)

[Philip Reames via llvm-commits]

https://github.com/preames commented:

So, I think this is generally the right direction, and am very supportive of the work.

However, I want to suggest a code structure change.  I think we need to split the current isTriviallyReMaterializable into two.  Version 1 keeps the current behavior.  Version 2 explicitly allows the virtual regs, and the caller takes the responsibility for checking liveness. 

As was discussed in the old phabricator review, I think there's an important difference between "we know this instruction is going to be materializeable in the future", and "we know this instruction is rematerializeable right now".  The later question gets to use a a lot more information.

The tricky bit is that I think we *already* have this distinction in the current code, and just don't realize it.  Several of the backends (AMDGPU, RISC-V for vector ops) already allow rematerialization of instructions with live virt regs!

My suggestion would be something along the line of removing Trivially from the name of isTriviallyReMaterializable, and instead pass a boolean argument named "DisallowVRegUses".  Most callers pass true, with the one in LRE passing false.  

This also allows targets to "opt in" to the new behavior.  Benchmarks that want to keep the old behavior could unconditionally pass true to the generic implementation in their target hook.  

https://github.com/llvm/llvm-project/pull/159211