[llvm] [RISCV] Implement computeKnownBitsForTargetNode for SHL_ADD (PR #159105)

[Craig Topper via llvm-commits]

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@@ -21561,6 +21561,15 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
     Known = Known.sext(BitWidth);
     break;
   }
+  case RISCVISD::SHL_ADD: {
+    KnownBits Known2;
+    Known = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
+    Known2 = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
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topperc wrote:

> Done. I assume you meant `<<=` and `setLowBits`.

I did. Sorry about that.

https://github.com/llvm/llvm-project/pull/159105