[llvm] AMDGPU: Constrain regclass when replacing SGPRs with VGPRs (PR #159369)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/159369

We need to account for local instruction constraints after
finding a replacement VGPR class. This solves expensive_checks
failures in existing tests.

>From d837801764c7c8777e7c98a9019731049f637cf6 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Wed, 17 Sep 2025 22:55:19 +0900
Subject: [PATCH] AMDGPU: Constrain regclass when replacing SGPRs with VGPRs

We need to account for local instruction constraints after
finding a replacement VGPR class. This solves expensive_checks
failures in existing tests.
---
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index c39da779ecf8c..37c75fe7f7dfd 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -8993,7 +8993,10 @@ void SIInstrInfo::addUsersToMoveToVALUWorklist(
       break;
     }
 
-    if (!RI.hasVectorRegisters(getOpRegClass(UseMI, OpNo)))
+    const TargetRegisterClass *OpRC = getOpRegClass(UseMI, OpNo);
+    MRI.constrainRegClass(DstReg, OpRC);
+
+    if (!RI.hasVectorRegisters(OpRC))
       Worklist.insert(&UseMI);
     else
       // Legalization could change user list.