[llvm] [Mips] Fix clang crashes when assembling invalid MIPS beql instructions with --arch=mips (PR #156413)

[via llvm-commits]

https://github.com/yingopq updated https://github.com/llvm/llvm-project/pull/156413

>From 5c8d18d789f15649e3365caee8dedca19053ded1 Mon Sep 17 00:00:00 2001
From: Ying Huang <ying.huang at oss.cipunited.com>
Date: Mon, 1 Sep 2025 22:38:25 -0400
Subject: [PATCH] [Mips] Fix clang crashes when assembling invalid MIPS beql
 instructions with --arch=mips

>From clang version 4, mips append new instruction BeqImm and
BEQLImmMacro, the second operand of instruction format is imm64:$imm.

1.When Mips process `beql $t0, ($t0), 1`, it think the second operand
was an imm, so match success. Then mips backend process expandBranchImm,
check the Operand(1) was not imm, reported asserts.
We can strengthen the second operand matching restrictions.

2.Similarly, when Mips process `beql $t0, (1), 1`, it think the second
was an imm. so match success. Then mips backend process expandBranchImm,
check the Operand(2) was not expression, reported asserts.
We can strengthen the third operand matching restrictions.

Fix #151453.
---
 llvm/lib/Target/Mips/MipsInstrInfo.td | 32 ++++++++++++++++++++++++---
 1 file changed, 29 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index a124e84e9ca5f..49c200d6f9dbe 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -829,12 +829,28 @@ def MipsJumpTargetAsmOperand : AsmOperandClass {
   let RenderMethod = "addImmOperands";
 }
 
+def MipsMemJumpTargetAsmOperand : AsmOperandClass {
+  let Name = "MemJumpTarget";
+  let ParserMethod = "parseJumpTarget";
+  let PredicateMethod = "isConstantMemOff";
+  let RenderMethod = "addImmOperands";
+}
+
 // Instruction operand types
 def jmptarget   : Operand<OtherVT> {
   let EncoderMethod = "getJumpTargetOpValue";
   let ParserMatchClass = MipsJumpTargetAsmOperand;
   let PrintMethod = "printJumpOperand";
 }
+
+def Membrtarget    : Operand<OtherVT> {
+  let EncoderMethod = "getBranchTargetOpValue";
+  let OperandType = "OPERAND_PCREL";
+  let DecoderMethod = "DecodeBranchTarget";
+  let ParserMatchClass = MipsMemJumpTargetAsmOperand;
+  let PrintMethod = "printBranchOperand";
+}
+
 def brtarget    : Operand<OtherVT> {
   let EncoderMethod = "getBranchTargetOpValue";
   let OperandType = "OPERAND_PCREL";
@@ -857,6 +873,16 @@ def calltarget  : Operand<iPTR> {
 
 def imm64: Operand<i64>;
 
+def ConstantImmAsmOperandClass : AsmOperandClass {
+  let Name = "ConstantImm";
+  let PredicateMethod = "isConstantImm";
+  let RenderMethod = "addImmOperands";
+}
+
+def ConstantImm64: Operand<i64> {
+  let ParserMatchClass = ConstantImmAsmOperandClass;
+}
+
 def simm19_lsl2 : Operand<i32> {
   let EncoderMethod = "getSimm19Lsl2Encoding";
   let DecoderMethod = "DecodeSimm19Lsl2";
@@ -2949,10 +2975,10 @@ def : MipsInstAlias<"nor\t$rs, $imm", (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs,
 
 let hasDelaySlot = 1, isCTI = 1 in {
 def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
-                               (ins imm64:$imm64, brtarget:$offset),
+                               (ins ConstantImm64:$imm64, Membrtarget:$offset),
                                "bne\t$rt, $imm64, $offset">;
 def BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
-                               (ins imm64:$imm64, brtarget:$offset),
+                               (ins ConstantImm64:$imm64, Membrtarget:$offset),
                                "beq\t$rt, $imm64, $offset">;
 
 class CondBranchPseudo<string instr_asm> :
@@ -2980,7 +3006,7 @@ def BGTUL: CondBranchPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
 
 let isCTI = 1 in
 class CondBranchImmPseudo<string instr_asm> :
-  MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, imm64:$imm, brtarget:$offset),
+  MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, ConstantImm64:$imm, Membrtarget:$offset),
                     !strconcat(instr_asm, "\t$rs, $imm, $offset")>;
 
 def BEQLImmMacro : CondBranchImmPseudo<"beql">, ISA_MIPS2_NOT_32R6_64R6;