[llvm] [RISCV] Add isel for bitcasting between bfloat and half types (PR #158828)

[via llvm-commits]

https://github.com/yingwang-bj updated https://github.com/llvm/llvm-project/pull/158828

>From 2cf9bacee22b74ec14d88e464082056a896808b5 Mon Sep 17 00:00:00 2001
From: Ying Wang <wy446777 at alibaba-inc.com>
Date: Tue, 16 Sep 2025 16:12:44 +0800
Subject: [PATCH] [RISCV] Add isel for bitcasting between bfloat and half types

---
 .../lib/Target/RISCV/RISCVInstrInfoZfbfmin.td |  7 +++++
 .../test/CodeGen/RISCV/bfloat-convert-half.ll | 29 +++++++++++++++++++
 2 files changed, 36 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/bfloat-convert-half.ll

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
index 8f0768f91c370..cdb43b11dd922 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
@@ -70,3 +70,10 @@ def : Pat<(bf16 (fpround FPR64:$rs1)),
 def : Pat<(fpextend (bf16 FPR16:$rs1)),
           (FCVT_D_S (FCVT_S_BF16 FPR16:$rs1, FRM_DYN), FRM_RNE)>;
 }
+
+let Predicates = [HasStdExtZfhmin, HasStdExtZfbfmin] in {
+// bf16 -> f16
+def : Pat<(f16 (bitconvert (bf16 FPR16:$src))), (f16 FPR16:$src)>;
+// f16 -> bf16
+def : Pat<(bf16 (bitconvert (f16 FPR16:$src))), (bf16 FPR16:$src)>;
+}
diff --git a/llvm/test/CodeGen/RISCV/bfloat-convert-half.ll b/llvm/test/CodeGen/RISCV/bfloat-convert-half.ll
new file mode 100644
index 0000000000000..789b538cdc286
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/bfloat-convert-half.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+Zfhmin,+Zfbfmin \
+; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+Zfhmin,+Zfbfmin \
+; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=RV64
+
+define bfloat @fcvt_bf16_h(half %a) nounwind {
+; RV32-LABEL: fcvt_bf16_h:
+; RV32:       # %bb.0:
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: fcvt_bf16_h:
+; RV64:       # %bb.0:
+; RV64-NEXT:    ret
+  %r = bitcast half %a to bfloat
+  ret bfloat %r
+}
+
+define half @test_h_bf16(bfloat %a) nounwind {
+; RV32-LABEL: test_h_bf16:
+; RV32:       # %bb.0:
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: test_h_bf16:
+; RV64:       # %bb.0:
+; RV64-NEXT:    ret
+  %r = bitcast bfloat %a to half
+  ret half %r
+}