[llvm] b22448c - [PowerPC] Add intrinsic definition for load and store with Right Length Left-justified (#148873)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 16 09:36:31 PDT 2025
Author: Lei Huang
Date: 2025-09-16T12:36:28-04:00
New Revision: b22448c9ba90efb3a2a6a7bdb8ffeeee9fcabb62
URL: https://github.com/llvm/llvm-project/commit/b22448c9ba90efb3a2a6a7bdb8ffeeee9fcabb62
DIFF: https://github.com/llvm/llvm-project/commit/b22448c9ba90efb3a2a6a7bdb8ffeeee9fcabb62.diff
LOG: [PowerPC] Add intrinsic definition for load and store with Right Length Left-justified (#148873)
Added:
llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
Modified:
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrFuture.td
Removed:
################################################################################
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index fb97230e0f8eb..636e88898a55e 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1358,6 +1358,18 @@ def int_ppc_vsx_lxvll :
def int_ppc_vsx_lxvp :
DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_ptr_ty],
[IntrReadMem, IntrArgMemOnly]>;
+def int_ppc_vsx_lxvrl :
+ DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i64_ty],
+ [IntrReadMem, IntrArgMemOnly]>;
+def int_ppc_vsx_lxvrll :
+ DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i64_ty],
+ [IntrReadMem, IntrArgMemOnly]>;
+def int_ppc_vsx_lxvprl :
+ DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_ptr_ty, llvm_i64_ty],
+ [IntrReadMem, IntrArgMemOnly]>;
+def int_ppc_vsx_lxvprll :
+ DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_ptr_ty, llvm_i64_ty],
+ [IntrReadMem, IntrArgMemOnly]>;
// Vector store.
def int_ppc_vsx_stxvw4x : Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
@@ -1377,6 +1389,19 @@ def int_ppc_vsx_stxvll :
def int_ppc_vsx_stxvp :
Intrinsic<[], [llvm_v256i1_ty, llvm_ptr_ty], [IntrWriteMem,
IntrArgMemOnly]>;
+def int_ppc_vsx_stxvrl :
+ Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty],
+ [IntrWriteMem, IntrArgMemOnly]>;
+def int_ppc_vsx_stxvrll :
+ Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty],
+ [IntrWriteMem, IntrArgMemOnly]>;
+def int_ppc_vsx_stxvprl :
+ Intrinsic<[], [llvm_v256i1_ty, llvm_ptr_ty, llvm_i64_ty], [IntrWriteMem,
+ IntrArgMemOnly]>;
+def int_ppc_vsx_stxvprll :
+ Intrinsic<[], [llvm_v256i1_ty, llvm_ptr_ty, llvm_i64_ty], [IntrWriteMem,
+ IntrArgMemOnly]>;
+
// Vector and scalar maximum.
def int_ppc_vsx_xvmaxdp : PowerPC_VSX_Vec_DDD_Intrinsic<"xvmaxdp">;
def int_ppc_vsx_xvmaxsp : PowerPC_VSX_Vec_FFF_Intrinsic<"xvmaxsp">;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index a12dfae2a0d7f..5751d7dc1628b 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -192,3 +192,21 @@ let Predicates = [HasVSX, IsISAFuture] in {
: VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
"vucmprlh $VRT, $VRA, $VRB", []>;
}
+
+//---------------------------- Anonymous Patterns ----------------------------//
+
+// Load/Store VSX Vector with Right Length (Left-justified).
+def : Pat<(v4i32 (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)), (LXVRL $RA, $RB)>;
+def : Pat<(v4i32 (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)), (LXVRLL $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB), (STXVRL $XT, $RA,
+ $RB)>;
+def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB), (STXVRLL $XT, $RA,
+ $RB)>;
+
+// Load/Store VSX Vector pair with Right Length (Left-justified).
+def : Pat<(v256i1 (int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
+def : Pat<(v256i1 (int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvprl v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRL $XTp,
+ $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRLL $XTp,
+ $RA, $RB)>;
diff --git a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
new file mode 100644
index 0000000000000..e7bc8fbca3202
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
@@ -0,0 +1,157 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
+; RUN: FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
+; RUN: FileCheck %s --check-prefix=AIX
+
+; Test for load/store to/from v4i32.
+
+define <4 x i32> @testLXVRL(ptr %a, i64 %b) {
+; CHECK-LABEL: testLXVRL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxvrl v2, r3, r4
+; CHECK-NEXT: blr
+;
+; AIX-LABEL: testLXVRL:
+; AIX: # %bb.0: # %entry
+; AIX-NEXT: lxvrl v2, r3, r4
+; AIX-NEXT: blr
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvrl(ptr %a, i64 %b)
+ ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.vsx.lxvrl(ptr, i64)
+
+define <4 x i32> @testLXVRLL(ptr %a, i64 %b) {
+; CHECK-LABEL: testLXVRLL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxvrll v2, r3, r4
+; CHECK-NEXT: blr
+;
+; AIX-LABEL: testLXVRLL:
+; AIX: # %bb.0: # %entry
+; AIX-NEXT: lxvrll v2, r3, r4
+; AIX-NEXT: blr
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvrll(ptr %a, i64 %b)
+ ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.vsx.lxvrll(ptr, i64)
+
+define void @testSTXVRL(<4 x i32> %a, ptr %b, i64 %c) {
+; CHECK-LABEL: testSTXVRL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stxvrl v2, r5, r6
+; CHECK-NEXT: blr
+;
+; AIX-LABEL: testSTXVRL:
+; AIX: # %bb.0: # %entry
+; AIX-NEXT: stxvrl v2, r3, r4
+; AIX-NEXT: blr
+entry:
+ tail call void @llvm.ppc.vsx.stxvrl(<4 x i32> %a, ptr %b, i64 %c)
+ ret void
+}
+declare void @llvm.ppc.vsx.stxvrl(<4 x i32>, ptr, i64)
+
+define void @testSTXVRLL(<4 x i32> %a, ptr %b, i64 %c) {
+; CHECK-LABEL: testSTXVRLL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stxvrll v2, r5, r6
+; CHECK-NEXT: blr
+;
+; AIX-LABEL: testSTXVRLL:
+; AIX: # %bb.0: # %entry
+; AIX-NEXT: stxvrll v2, r3, r4
+; AIX-NEXT: blr
+entry:
+ tail call void @llvm.ppc.vsx.stxvrll(<4 x i32> %a, ptr %b, i64 %c)
+ ret void
+}
+declare void @llvm.ppc.vsx.stxvrll(<4 x i32>, ptr, i64)
+
+; Test for load/store vectore pair.
+
+define <256 x i1> @testLXVPRL(ptr %vpp, i64 %b) {
+; CHECK-LABEL: testLXVPRL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxvprl vsp34, r4, r5
+; CHECK-NEXT: stxv v2, 16(r3)
+; CHECK-NEXT: stxv v3, 0(r3)
+; CHECK-NEXT: blr
+;
+; AIX-LABEL: testLXVPRL:
+; AIX: # %bb.0: # %entry
+; AIX-NEXT: lxvprl vsp34, r4, r5
+; AIX-NEXT: stxv v3, 16(r3)
+; AIX-NEXT: stxv v2, 0(r3)
+; AIX-NEXT: blr
+entry:
+ %0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprl(ptr %vpp, i64 %b)
+ ret <256 x i1> %0
+}
+declare <256 x i1> @llvm.ppc.vsx.lxvprl(ptr, i64)
+
+define <256 x i1> @testLXVPRLL(ptr %vpp, i64 %b) {
+; CHECK-LABEL: testLXVPRLL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxvprll vsp34, r4, r5
+; CHECK-NEXT: stxv v2, 16(r3)
+; CHECK-NEXT: stxv v3, 0(r3)
+; CHECK-NEXT: blr
+;
+; AIX-LABEL: testLXVPRLL:
+; AIX: # %bb.0: # %entry
+; AIX-NEXT: lxvprll vsp34, r4, r5
+; AIX-NEXT: stxv v3, 16(r3)
+; AIX-NEXT: stxv v2, 0(r3)
+; AIX-NEXT: blr
+entry:
+ %0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprll(ptr %vpp, i64 %b)
+ ret <256 x i1> %0
+}
+declare <256 x i1> @llvm.ppc.vsx.lxvprll(ptr, i64)
+
+define void @testSTXVPRL(ptr %v, ptr %vp, i64 %len) {
+; CHECK-LABEL: testSTXVPRL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxv v2, 16(r3)
+; CHECK-NEXT: lxv v3, 0(r3)
+; CHECK-NEXT: stxvprl vsp34, r4, r5
+; CHECK-NEXT: blr
+;
+; AIX-LABEL: testSTXVPRL:
+; AIX: # %bb.0: # %entry
+; AIX-NEXT: lxv v2, 0(r3)
+; AIX-NEXT: lxv v3, 16(r3)
+; AIX-NEXT: stxvprl vsp34, r4, r5
+; AIX-NEXT: blr
+entry:
+ %0 = load <256 x i1>, ptr %v, align 32
+ tail call void @llvm.ppc.vsx.stxvprl(<256 x i1> %0, ptr %vp, i64 %len)
+ ret void
+}
+declare void @llvm.ppc.vsx.stxvprl(<256 x i1>, ptr, i64)
+
+define void @testSTXVPRLL(ptr %v, ptr %vp, i64 %len) {
+; CHECK-LABEL: testSTXVPRLL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxv v2, 16(r3)
+; CHECK-NEXT: lxv v3, 0(r3)
+; CHECK-NEXT: stxvprll vsp34, r4, r5
+; CHECK-NEXT: blr
+;
+; AIX-LABEL: testSTXVPRLL:
+; AIX: # %bb.0: # %entry
+; AIX-NEXT: lxv v2, 0(r3)
+; AIX-NEXT: lxv v3, 16(r3)
+; AIX-NEXT: stxvprll vsp34, r4, r5
+; AIX-NEXT: blr
+entry:
+ %0 = load <256 x i1>, ptr %v, align 32
+ tail call void @llvm.ppc.vsx.stxvprll(<256 x i1> %0, ptr %vp, i64 %len)
+ ret void
+}
+declare void @llvm.ppc.vsx.stxvprll(<256 x i1>, ptr, i64)
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