[llvm] [AArch64] Unfold adds when eliminating frame index with scalable offset (PR #158597)
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 16 03:19:30 PDT 2025
================
@@ -0,0 +1,154 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64 -run-pass prologepilog -o - %s | FileCheck %s
+--- |
+ define void @i(ptr %ad, ptr %0) #0 {
+ entry:
+ ret void
+ }
+ declare i32 @g(...)
+ attributes #0 = { "frame-pointer"="non-leaf" "target-features"="+sve" }
+...
+---
+name: i
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+noPhis: true
+isSSA: false
+noVRegs: true
+hasFakeUses: false
+callsEHReturn: false
+callsUnwindInit: false
+hasEHContTarget: false
+hasEHScopes: false
+hasEHFunclets: false
+isOutlined: false
+debugInstrRef: false
+failsVerification: false
+tracksDebugUserValues: true
+registers: []
+liveins: []
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 16
+ adjustsStack: true
+ hasCalls: true
+ stackProtector: ''
+ functionContext: ''
+ maxCallFrameSize: 0
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ hasTailCall: false
+ isCalleeSavedInfoValid: false
+ localFrameSize: 0
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: default, offset: 0, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+ local-offset: -4, debug-info-variable: '', debug-info-expression: '',
+ debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 8,
+ stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 2, name: '', type: spill-slot, offset: 0, size: 8, alignment: 8,
+ stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 3, name: '', type: spill-slot, offset: 0, size: 16, alignment: 16,
+ stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+entry_values: []
+callSites: []
+debugValueSubstitutions: []
+constants: []
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: i
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)
+ ; CHECK-NEXT: liveins: $x0, $x1, $d11, $lr, $x19, $x28
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber $sp = frame-setup STRDpre killed $d11, $sp, -48 :: (store (s64) into %stack.8)
+ ; CHECK-NEXT: frame-setup STPXi killed $fp, killed $lr, $sp, 2 :: (store (s64) into %stack.7), (store (s64) into %stack.6)
+ ; CHECK-NEXT: frame-setup STPXi killed $x28, killed $x19, $sp, 4 :: (store (s64) into %stack.5), (store (s64) into %stack.4)
+ ; CHECK-NEXT: $fp = frame-setup ADDXri $sp, 16, 0
+ ; CHECK-NEXT: $sp = frame-setup SUBXri $sp, 16, 0
+ ; CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -1, implicit $vg
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $w29, 32
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w19, -8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w28, -16
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w30, -24
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -32
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $b11, -48
+ ; CHECK-NEXT: B %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1 (inlineasm-br-indirect-target):
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $w19 = MOVi32imm 1
+ ; CHECK-NEXT: B %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors:
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3 (inlineasm-br-indirect-target):
+ ; CHECK-NEXT: successors: %bb.4(0x80000000), %bb.3(0x00000000)
+ ; CHECK-NEXT: liveins: $w19
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $q11
+ ; CHECK-NEXT: B %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: liveins: $w19
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: BL @g, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $w0
+ ; CHECK-NEXT: $x8 = ADDXri $sp, 28, 0
+ ; CHECK-NEXT: $x8 = ADDVL_XXI $x8, 1, implicit $vg
+ ; CHECK-NEXT: $x8 = ADDSXri $x8, 0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: B %bb.3
+ bb.0:
+ successors: %bb.2(0x80000000), %bb.1(0x00000000)
+ liveins: $x0, $x1
+
+ B %bb.2
+
+ bb.1 (inlineasm-br-indirect-target):
+ successors: %bb.3(0x80000000)
+ liveins: $x0, $x1
+
+ renamable $w19 = MOVi32imm 1
+ B %bb.3
+
+ bb.2:
+ successors:
+
+ bb.3 (inlineasm-br-indirect-target):
+ successors: %bb.4(0x80000000), %bb.3(0x00000000)
+ liveins: $w19
+
+ INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $q11
+ B %bb.4
+
+ bb.4:
+ successors: %bb.3(0x80000000)
+ liveins: $w19
+
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ BL @g, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $w0
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ dead renamable $x8 = ADDSXri %stack.0, 0, 0, implicit-def $nzcv
----------------
sdesmalen-arm wrote:
I appreciate you making an MIR test, but this function has a lot going on that isn't relevant to the thing we actually want to test, and so it is not really a reduced test-case yet. Can you simplify this further? (I'd recommend just writing an MIR test manually, without all the control flow and a simple `ADDSXri` instruction like you have here)
https://github.com/llvm/llvm-project/pull/158597
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