[llvm] [LoongArch] Fix instruction selection failure for BUILD_VECTOR on LA32 (PR #158788)
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llvm-commits at lists.llvm.org
Tue Sep 16 02:30:07 PDT 2025
https://github.com/heiher updated https://github.com/llvm/llvm-project/pull/158788
>From 3dcf17d7827b96a6c942fa163c9f98a54f4cd433 Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui at loongson.cn>
Date: Tue, 16 Sep 2025 14:05:29 +0800
Subject: [PATCH] [LoongArch] Fix instruction selection failure for
BUILD_VECTOR on LA32
---
.../LoongArch/LoongArchISelLowering.cpp | 5 +-
.../CodeGen/LoongArch/lasx/build-vector.ll | 86 ++++++++++++++++---
.../CodeGen/LoongArch/lsx/build-vector.ll | 86 ++++++++++++++++---
3 files changed, 147 insertions(+), 30 deletions(-)
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 634914d3b3fd0..5109744a79913 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -2671,8 +2671,9 @@ SDValue LoongArchTargetLowering::lowerBUILD_VECTOR(SDValue Op,
if (SplatBitSize == 64 && !Subtarget.is64Bit()) {
// We can only handle 64-bit elements that are within
- // the signed 32-bit range on 32-bit targets.
- if (!SplatValue.isSignedIntN(32))
+ // the signed 10-bit range on 32-bit targets.
+ // See the BUILD_VECTOR case in LoongArchDAGToDAGISel::Select().
+ if (!SplatValue.isSignedIntN(10))
return SDValue();
if ((Is128Vec && ResTy == MVT::v4i32) ||
(Is256Vec && ResTy == MVT::v8i32))
diff --git a/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll b/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
index 23245726c8968..d6756b9395237 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
@@ -106,6 +106,26 @@ entry:
ret void
}
+define void @buildvector_v32i8_const_splat_v4i64(ptr %dst) nounwind {
+; LA32-LABEL: buildvector_v32i8_const_splat_v4i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI7_0)
+; LA32-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI7_0)
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v32i8_const_splat_v4i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: lu12i.w $a1, 7
+; LA64-NEXT: ori $a1, $a1, 3453
+; LA64-NEXT: xvreplgr2vr.d $xr0, $a1
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
+entry:
+ store <32 x i8> <i8 125, i8 125, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 125, i8 125, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 125, i8 125, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 125, i8 125, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, ptr %dst
+ ret void
+}
+
define void @buildvector_v16i16_const_splat(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v16i16_const_splat:
; CHECK: # %bb.0: # %entry
@@ -117,6 +137,25 @@ entry:
ret void
}
+define void @buildvector_v16i16_const_splat_v4i64(ptr %dst) nounwind {
+; LA32-LABEL: buildvector_v16i16_const_splat_v4i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI9_0)
+; LA32-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI9_0)
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v16i16_const_splat_v4i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ori $a1, $zero, 512
+; LA64-NEXT: xvreplgr2vr.d $xr0, $a1
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
+entry:
+ store <16 x i16> <i16 512, i16 0, i16 0, i16 0, i16 512, i16 0, i16 0, i16 0, i16 512, i16 0, i16 0, i16 0, i16 512, i16 0, i16 0, i16 0>, ptr %dst
+ ret void
+}
+
define void @buildvector_v8i32_const_splat(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v8i32_const_splat:
; CHECK: # %bb.0: # %entry
@@ -128,6 +167,25 @@ entry:
ret void
}
+define void @buildvector_v8i32_const_splat_v4i64(ptr %dst) nounwind {
+; LA32-LABEL: buildvector_v8i32_const_splat_v4i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)
+; LA32-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI11_0)
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v8i32_const_splat_v4i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ori $a1, $zero, 512
+; LA64-NEXT: xvreplgr2vr.d $xr0, $a1
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
+entry:
+ store <8 x i32> <i32 512, i32 0, i32 512, i32 0, i32 512, i32 0, i32 512, i32 0>, ptr %dst
+ ret void
+}
+
define void @buildvector_v4i64_const_splat(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v4i64_const_splat:
; CHECK: # %bb.0: # %entry
@@ -154,8 +212,8 @@ entry:
define void @buildvector_v4f64_const_splat(ptr %dst) nounwind {
; LA32-LABEL: buildvector_v4f64_const_splat:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)
-; LA32-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI11_0)
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI14_0)
+; LA32-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI14_0)
; LA32-NEXT: xvst $xr0, $a0, 0
; LA32-NEXT: ret
;
@@ -173,8 +231,8 @@ entry:
define void @buildvector_v32i8_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v32i8_const:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI12_0)
-; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI12_0)
+; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI15_0)
+; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI15_0)
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
@@ -185,8 +243,8 @@ entry:
define void @buildvector_v16i16_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v16i16_const:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI13_0)
-; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI13_0)
+; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI16_0)
+; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI16_0)
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
@@ -197,8 +255,8 @@ entry:
define void @buildvector_v8i32_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v8i32_const:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI14_0)
-; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI14_0)
+; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI17_0)
+; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI17_0)
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
@@ -209,8 +267,8 @@ entry:
define void @buildvector_v4i64_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v4i64_const:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI15_0)
-; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI15_0)
+; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI18_0)
+; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI18_0)
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
@@ -221,8 +279,8 @@ entry:
define void @buildvector_v2f32_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v2f32_const:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI16_0)
-; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI16_0)
+; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI19_0)
+; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI19_0)
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
@@ -233,8 +291,8 @@ entry:
define void @buildvector_v4f64_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v4f64_const:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI17_0)
-; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI17_0)
+; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI20_0)
+; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI20_0)
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll b/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll
index 24df71c2ad71b..ac28151dc2f54 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll
@@ -102,6 +102,26 @@ entry:
ret void
}
+define void @buildvector_v16i8_const_splat_v2i64(ptr %dst) nounwind {
+; LA32-LABEL: buildvector_v16i8_const_splat_v2i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI7_0)
+; LA32-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI7_0)
+; LA32-NEXT: vst $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v16i8_const_splat_v2i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: lu12i.w $a1, 7
+; LA64-NEXT: ori $a1, $a1, 3453
+; LA64-NEXT: vreplgr2vr.d $vr0, $a1
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
+entry:
+ store <16 x i8> <i8 125, i8 125, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 125, i8 125, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, ptr %dst
+ ret void
+}
+
define void @buildvector_v8i16_const_splat(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v8i16_const_splat:
; CHECK: # %bb.0: # %entry
@@ -113,6 +133,25 @@ entry:
ret void
}
+define void @buildvector_v8i16_const_splat_v2i64(ptr %dst) nounwind {
+; LA32-LABEL: buildvector_v8i16_const_splat_v2i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI9_0)
+; LA32-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI9_0)
+; LA32-NEXT: vst $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v8i16_const_splat_v2i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ori $a1, $zero, 512
+; LA64-NEXT: vreplgr2vr.d $vr0, $a1
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
+entry:
+ store <8 x i16> <i16 512, i16 0, i16 0, i16 0, i16 512, i16 0, i16 0, i16 0>, ptr %dst
+ ret void
+}
+
define void @buildvector_v4i32_const_splat(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v4i32_const_splat:
; CHECK: # %bb.0: # %entry
@@ -124,6 +163,25 @@ entry:
ret void
}
+define void @buildvector_v4i32_const_splat_v2i64(ptr %dst) nounwind {
+; LA32-LABEL: buildvector_v4i32_const_splat_v2i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)
+; LA32-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI11_0)
+; LA32-NEXT: vst $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v4i32_const_splat_v2i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ori $a1, $zero, 512
+; LA64-NEXT: vreplgr2vr.d $vr0, $a1
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
+entry:
+ store <4 x i32> <i32 512, i32 0, i32 512, i32 0>, ptr %dst
+ ret void
+}
+
define void @buildvector_v2i64_const_splat(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v2i64_const_splat:
; CHECK: # %bb.0: # %entry
@@ -150,8 +208,8 @@ entry:
define void @buildvector_v2f64_const_splat(ptr %dst) nounwind {
; LA32-LABEL: buildvector_v2f64_const_splat:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)
-; LA32-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI11_0)
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI14_0)
+; LA32-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI14_0)
; LA32-NEXT: vst $vr0, $a0, 0
; LA32-NEXT: ret
;
@@ -169,8 +227,8 @@ entry:
define void @buildvector_v16i8_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v16i8_const:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI12_0)
-; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI12_0)
+; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI15_0)
+; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI15_0)
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
@@ -181,8 +239,8 @@ entry:
define void @buildvector_v8i16_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v8i16_const:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI13_0)
-; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI13_0)
+; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI16_0)
+; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI16_0)
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
@@ -193,8 +251,8 @@ entry:
define void @buildvector_v4i32_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v4i32_const:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI14_0)
-; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI14_0)
+; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI17_0)
+; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI17_0)
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
@@ -205,8 +263,8 @@ entry:
define void @buildvector_v2i64_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v2i64_const:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI15_0)
-; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI15_0)
+; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI18_0)
+; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI18_0)
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
@@ -217,8 +275,8 @@ entry:
define void @buildvector_v2f32_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v2f32_const:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI16_0)
-; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI16_0)
+; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI19_0)
+; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI19_0)
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
@@ -229,8 +287,8 @@ entry:
define void @buildvector_v2f64_const(ptr %dst) nounwind {
; CHECK-LABEL: buildvector_v2f64_const:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI17_0)
-; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI17_0)
+; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI20_0)
+; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI20_0)
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
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