[llvm] [RISCV] Add hasREV8Like helper to RISCVSubtarget. NFC (PR #158775)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 15 21:48:09 PDT 2025
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/158775
None
>From 137ec5c110a683ffefac29bf5ee83f7883649b8d Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 15 Sep 2025 21:25:02 -0700
Subject: [PATCH] [RISCV] Add hasREV8Like helper to RISCVSubtarget. NFC
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 7 +------
llvm/lib/Target/RISCV/RISCVSubtarget.h | 3 +++
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 5485b916c2031..f5bb70b8a93e0 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -378,13 +378,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Expand);
}
- // With Zbb we have an XLen rev8 instruction, but not GREVI. So we'll
- // pattern match it directly in isel.
setOperationAction(ISD::BSWAP, XLenVT,
- (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb() ||
- Subtarget.hasVendorXTHeadBb())
- ? Legal
- : Expand);
+ Subtarget.hasREV8Like() ? Legal : Expand);
if ((Subtarget.hasVendorXCVbitmanip() || Subtarget.hasVendorXqcibm()) &&
!Subtarget.is64Bit()) {
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 0d9cd16a77937..d4aca90816d81 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -196,6 +196,9 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool hasCPOPLike() const {
return HasStdExtZbb || (HasVendorXCVbitmanip && !IsRV64);
}
+ bool hasREV8Like() const {
+ return HasStdExtZbb | HasStdExtZbkb || HasVendorXTHeadBb;
+ }
bool hasBEXTILike() const { return HasStdExtZbs || HasVendorXTHeadBs; }
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