[llvm] 9bedece - [LegalizeTypes] Use correct type for constant in PromoteIntRes_FunnelShift.

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Mon Sep 15 15:55:03 PDT 2025


Author: Craig Topper
Date: 2025-09-15T15:54:26-07:00
New Revision: 9bedece621aec7d6b35836e6896abdb54940dfdf

URL: https://github.com/llvm/llvm-project/commit/9bedece621aec7d6b35836e6896abdb54940dfdf
DIFF: https://github.com/llvm/llvm-project/commit/9bedece621aec7d6b35836e6896abdb54940dfdf.diff

LOG: [LegalizeTypes] Use correct type for constant in PromoteIntRes_FunnelShift.

This is a typo from #158553. We should use AmtVT instead of VT.

I guess VT and AmtVT are always the same at this point for tested
targets.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index ba424198ad5b7..88a4a8b16373b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1631,7 +1631,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FunnelShift(SDNode *N) {
   // type.
   if (IsFSHR)
     Amt = DAG.getNode(ISD::ADD, DL, AmtVT, Amt,
-                      DAG.getConstant(NewBits - OldBits, DL, VT));
+                      DAG.getConstant(NewBits - OldBits, DL, AmtVT));
 
   return DAG.getNode(Opcode, DL, VT, Hi, Lo, Amt);
 }


        


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