[llvm] [llvm][RISCV] Implement Zilsd load/store pair optimization (PR #158640)

Sam Elliott via llvm-commits llvm-commits at lists.llvm.org
Mon Sep 15 10:26:27 PDT 2025


lenary wrote:

Great to see someone is contributing this work, as we have looked forward to having it too.

I have a few high-level comments, which I don't think are covered by Craig's review, and might supersede his comments:

Is this based on the NXP Patches against LLVM 18? If so, this will need appropriate Co-authored-by. Even if it isn't, I will add @anmolparalkar-nxp as a reviewer as he is familiar with that work.

We already have one pass that does this optimisation: `RISCVLoadStoreOptimizer` (in `PreSched2`). Your "PostAlloc" pass should be merged into this pass, as they are doing the same thing, at the same point in the pass pipeline (I will also add @djtodoro as a reviewer as he worked on that pass). The Pre Allocation pass can be left separate.

I am glad to see the new `zilsd-4byte-align` feature, as it is also something that we want, and would use in other places (e.g. #153595). I agree that this isn't a "tune" feature. To me it feels more similar to an intermediate scalar alignment mode, somewhere between "everything has to be naturally aligned" (the default) and `FeatureUnalignedScalarMem` (everything can be 1-byte aligned) - maybe it should be modelled that way? I guess we'd end up needing changes to clang flags to enable this, which can come as a follow-up.



https://github.com/llvm/llvm-project/pull/158640


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