[llvm] [llvm][RISCV] Implement Zilsd load/store pair optimization (PR #158640)

[Craig Topper via llvm-commits]

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@@ -194,6 +194,10 @@ def HasStdExtZilsd : Predicate<"Subtarget->hasStdExtZilsd()">,
                        AssemblerPredicate<(all_of FeatureStdExtZilsd),
                                           "'Zilsd' (Load/Store pair instructions)">;
 
+def TuneZilsd4ByteAlign
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topperc wrote:

This cannot be a "Tune" feature. If has to be part of mcpu not mtune. If the hardware doesn't support misaligned access it will crash. Tune features are not allowed to cause crashes.

https://github.com/llvm/llvm-project/pull/158640