[llvm] [llvm][RISCV] Implement Zilsd load/store pair optimization (PR #158640)

[Craig Topper via llvm-commits]

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@@ -853,6 +853,44 @@ bool RISCVRegisterInfo::getRegAllocationHints(
   const MachineRegisterInfo *MRI = &MF.getRegInfo();
   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
 
+  // Handle RegPairEven/RegPairOdd hints for Zilsd register pairs
+  std::pair<unsigned, Register> Hint = MRI->getRegAllocationHint(VirtReg);
+  unsigned HintType = Hint.first;
+  Register Partner = Hint.second;
+
+  if (HintType == RISCVRI::RegPairEven || HintType == RISCVRI::RegPairOdd) {
+    // Check if we want the even or odd register of a consecutive pair
+    bool WantOdd = (HintType == RISCVRI::RegPairOdd);
+
+    // First priority: Check if partner is already allocated
+    if (Partner.isVirtual() && VRM && VRM->hasPhys(Partner)) {
+      MCPhysReg PartnerPhys = VRM->getPhys(Partner);
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topperc wrote:

getPhy doesn't return `MCPhysReg`. It returns `MCRegister`. There's currently an implicit conversion operator from `MCRegister` to `unsigned`, but it is supposed to be removed in the future.

https://github.com/llvm/llvm-project/pull/158640