[llvm] [llvm][RISCV] Implement Zilsd load/store pair optimization (PR #158640)

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git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp llvm/lib/Target/RISCV/RISCV.h llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp llvm/lib/Target/RISCV/RISCVRegisterInfo.h llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
index 47d5abbbe..d4d6dd2f5 100644
--- a/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
@@ -621,7 +621,8 @@ bool RISCVPostAllocZilsdOpt::runOnMachineFunction(MachineFunction &MF) {
 
 bool RISCVPostAllocZilsdOpt::isConsecutiveRegPair(Register First,
                                                   Register Second) {
-  // Special case: both registers are zero register - this is valid for storing zeros
+  // Special case: both registers are zero register - this is valid for storing
+  // zeros
   if (First == RISCV::X0 && Second == RISCV::X0)
     return true;
 

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https://github.com/llvm/llvm-project/pull/158640