[llvm] [AMDGPU] Elide bitcast fold i64 imm to build_vector (PR #154115)

[Matt Arsenault via llvm-commits]

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@@ -5296,6 +5296,34 @@ SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,
   return DCI.DAG.getConstantFP(One / Val, SDLoc(N), N->getValueType(0));
 }
 
+bool AMDGPUTargetLowering::isInt64ImmLegal(SDNode *N, SelectionDAG &DAG) const {
+  if (!Subtarget->isGCN())
+    return false;
+
+  ConstantSDNode *SDConstant = dyn_cast<ConstantSDNode>(N);
+  ConstantFPSDNode *SDFPConstant = dyn_cast<ConstantFPSDNode>(N);
+  auto &ST = DAG.getSubtarget<GCNSubtarget>();
+  bool isInlineable = false;
+  const auto *TII = ST.getInstrInfo();
+
+  if (!SDConstant && !SDFPConstant)
+    return false;
+
+  uint64_t Val = 0;
+  if (SDConstant) {
+    const APInt &APVal = SDConstant->getAPIntValue();
+    isInlineable = TII->isInlineConstant(APVal);
+    Val = APVal.getZExtValue();
+  } else if (SDFPConstant) {
+    const APFloat &APVal = SDFPConstant->getValueAPF();
+    isInlineable = TII->isInlineConstant(APVal);
+    Val = APVal.bitcastToAPInt().getZExtValue();
+  }
+
+  return ST.hasMovB64() &&
+         (ST.has64BitLiterals() || isUInt<32>(Val) || isInlineable);
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arsenm wrote:

Can you shuffle this around such that the isInlineConstant is performed lazily 

https://github.com/llvm/llvm-project/pull/154115