[llvm] Allow Specifying SGMasks for Inline Asm (PR #155491)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> I haven't tried testing the inline assembly operands. I would be hesitant to do that because, although you know the architecture better than I do, I can't imagine every assembly instruction that uses a VGPR is a VALU instruction,

This is the case. There are 0 SALU instructions that can read or write a VGPR. The converse is almost true too; VALU instructions cannot write VGPRs, with the special cases of boolean flags, and readlane/writelane. But you don't need to have a perfect answer, it's still a scheduling heuristic decision. 

>  and "there's wrong behavior" seems worse than "there's no way to express what I want."

There cannot be wrong behavior in scheduling. The scheduling intrinsics can at most be interpreted as an optimization hint; optimizations cannot be semantics.

>  I can revert this PR back to that commit and then add the tests back if we decide to go that route.

Inline asm really is not a tool for improving performance and should not be treated as such. Inline assembly is a *hard break* of optimizations of the compiler. If anything we should be de-optimizing it harder (i.e. we could be conservatively resolving more hazards that exist inside inline assembly than we do today)



https://github.com/llvm/llvm-project/pull/155491