[llvm] 273917e - [AArch64] Update and extend some GlobalMerge tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 15 02:39:12 PDT 2025
Author: David Green
Date: 2025-09-15T10:39:07+01:00
New Revision: 273917e5c0d935af5736770bdc9d0b03ce04dd8c
URL: https://github.com/llvm/llvm-project/commit/273917e5c0d935af5736770bdc9d0b03ce04dd8c
DIFF: https://github.com/llvm/llvm-project/commit/273917e5c0d935af5736770bdc9d0b03ce04dd8c.diff
LOG: [AArch64] Update and extend some GlobalMerge tests. NFC
Added:
llvm/test/CodeGen/AArch64/global-merge-external.ll
Modified:
llvm/test/CodeGen/AArch64/aarch64-tail-dup-size.ll
llvm/test/CodeGen/AArch64/global-merge-minsize.ll
llvm/test/CodeGen/AArch64/local-bounds-single-trap.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/aarch64-tail-dup-size.ll b/llvm/test/CodeGen/AArch64/aarch64-tail-dup-size.ll
index be07404f4b2fc..f37c942ab950c 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-tail-dup-size.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-tail-dup-size.ll
@@ -4,7 +4,7 @@
; RUN: llc -mtriple=aarch64-none-linux -tail-dup-size=4 < %s | FileCheck %s --check-prefix=CHECK-O2
; RUN: llc -mtriple=aarch64-none-linux -tail-dup-placement-threshold=4 < %s | FileCheck %s --check-prefix=CHECK-O2
-; RUN: llc -mtriple=aarch64-none-linux -tail-dup-placement-threshold=6 < %s | FileCheck %s --check-prefix=CHECK-O3
+; RUN: llc -mtriple=aarch64-none-linux -tail-dup-placement-threshold=6 < %s | FileCheck %s --check-prefix=CHECK-O2-6
%a = type { ptr, i32, %b }
%b = type { %c }
@@ -29,7 +29,7 @@ define dso_local void @testcase(ptr nocapture %arg){
; CHECK-O2-NEXT: .LBB0_3: // %if.end
; CHECK-O2-NEXT: adrp x9, global_int
; CHECK-O2-NEXT: add x2, x8, #16
-; CHECK-O2-NEXT: mov w0, #10
+; CHECK-O2-NEXT: mov w0, #10 // =0xa
; CHECK-O2-NEXT: ldr w1, [x9, :lo12:global_int]
; CHECK-O2-NEXT: b externalfunc
;
@@ -44,16 +44,38 @@ define dso_local void @testcase(ptr nocapture %arg){
; CHECK-O3-NEXT: ldr x8, [x8, :lo12:global_ptr]
; CHECK-O3-NEXT: adrp x9, global_int
; CHECK-O3-NEXT: add x2, x8, #16
-; CHECK-O3-NEXT: mov w0, #10
+; CHECK-O3-NEXT: mov w0, #10 // =0xa
; CHECK-O3-NEXT: ldr w1, [x9, :lo12:global_int]
; CHECK-O3-NEXT: b externalfunc
; CHECK-O3-NEXT: .LBB0_2:
; CHECK-O3-NEXT: mov x8, xzr
; CHECK-O3-NEXT: adrp x9, global_int
; CHECK-O3-NEXT: add x2, x8, #16
-; CHECK-O3-NEXT: mov w0, #10
+; CHECK-O3-NEXT: mov w0, #10 // =0xa
; CHECK-O3-NEXT: ldr w1, [x9, :lo12:global_int]
; CHECK-O3-NEXT: b externalfunc
+;
+; CHECK-O2-6-LABEL: testcase:
+; CHECK-O2-6: // %bb.0: // %entry
+; CHECK-O2-6-NEXT: adrp x8, global_ptr
+; CHECK-O2-6-NEXT: ldr x9, [x8, :lo12:global_ptr]
+; CHECK-O2-6-NEXT: cbz x9, .LBB0_2
+; CHECK-O2-6-NEXT: // %bb.1: // %if.then
+; CHECK-O2-6-NEXT: ldr x9, [x9]
+; CHECK-O2-6-NEXT: str x9, [x0]
+; CHECK-O2-6-NEXT: ldr x8, [x8, :lo12:global_ptr]
+; CHECK-O2-6-NEXT: adrp x9, global_int
+; CHECK-O2-6-NEXT: add x2, x8, #16
+; CHECK-O2-6-NEXT: mov w0, #10 // =0xa
+; CHECK-O2-6-NEXT: ldr w1, [x9, :lo12:global_int]
+; CHECK-O2-6-NEXT: b externalfunc
+; CHECK-O2-6-NEXT: .LBB0_2:
+; CHECK-O2-6-NEXT: mov x8, xzr
+; CHECK-O2-6-NEXT: adrp x9, global_int
+; CHECK-O2-6-NEXT: add x2, x8, #16
+; CHECK-O2-6-NEXT: mov w0, #10 // =0xa
+; CHECK-O2-6-NEXT: ldr w1, [x9, :lo12:global_int]
+; CHECK-O2-6-NEXT: b externalfunc
entry:
%0 = load ptr, ptr @global_ptr, align 8
%cmp.not = icmp eq ptr %0, null
diff --git a/llvm/test/CodeGen/AArch64/global-merge-external.ll b/llvm/test/CodeGen/AArch64/global-merge-external.ll
new file mode 100644
index 0000000000000..fb3753c54e0ca
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/global-merge-external.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-O2
+; RUN: llc -O3 %s -o - -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-O3
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64"
+
+ at global0 = dso_local local_unnamed_addr global i32 0, align 4
+ at global1 = dso_local local_unnamed_addr global i32 0, align 4
+
+define dso_local i32 @func() {
+; CHECK-LABEL: func:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: adrp x8, global0
+; CHECK-NEXT: adrp x9, global1
+; CHECK-NEXT: ldr w8, [x8, :lo12:global0]
+; CHECK-NEXT: ldr w9, [x9, :lo12:global1]
+; CHECK-NEXT: add w0, w9, w8
+; CHECK-NEXT: ret
+entry:
+ %0 = load i32, ptr @global0, align 4
+ %1 = load i32, ptr @global1, align 4
+ %add = add nsw i32 %1, %0
+ ret i32 %add
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-O2: {{.*}}
+; CHECK-O3: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/global-merge-minsize.ll b/llvm/test/CodeGen/AArch64/global-merge-minsize.ll
index 8f569ecd9e634..f952580ba4540 100644
--- a/llvm/test/CodeGen/AArch64/global-merge-minsize.ll
+++ b/llvm/test/CodeGen/AArch64/global-merge-minsize.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
@@ -7,12 +8,13 @@ target triple = "aarch64"
@global1 = dso_local local_unnamed_addr global i32 0, align 4
define dso_local i32 @func() minsize optsize {
-; CHECK-LABEL: @func
-; CHECK: adrp x8, .L_MergedGlobals
-; CHECK-NEXT: add x8, x8, :lo12:.L_MergedGlobals
-; CHECK-NEXT: ldp w9, w8, [x8]
-; CHECK-NEXT: add w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-LABEL: func:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: adrp x8, .L_MergedGlobals
+; CHECK-NEXT: add x8, x8, :lo12:.L_MergedGlobals
+; CHECK-NEXT: ldp w9, w8, [x8]
+; CHECK-NEXT: add w0, w8, w9
+; CHECK-NEXT: ret
entry:
%0 = load i32, ptr @global0, align 4
%1 = load i32, ptr @global1, align 4
diff --git a/llvm/test/CodeGen/AArch64/local-bounds-single-trap.ll b/llvm/test/CodeGen/AArch64/local-bounds-single-trap.ll
index 8b8a3e430df69..caf6f1a83f762 100644
--- a/llvm/test/CodeGen/AArch64/local-bounds-single-trap.ll
+++ b/llvm/test/CodeGen/AArch64/local-bounds-single-trap.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -O3 -mtriple arm64-linux -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-ASM
; This test checks that nomerge correctly prevents the traps from being merged
; in the compiled code.
@@ -9,36 +10,44 @@
; Function Attrs: noinline nounwind uwtable
define dso_local void @f8(i32 noundef %i, i32 noundef %k) #0 {
+; CHECK-ASM-LABEL: f8:
+; CHECK-ASM: // %bb.0: // %entry
+; CHECK-ASM-NEXT: sub sp, sp, #16
+; CHECK-ASM-NEXT: .cfi_def_cfa_offset 16
+; CHECK-ASM-NEXT: .cfi_remember_state
+; CHECK-ASM-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-ASM-NEXT: sxtw x8, w0
+; CHECK-ASM-NEXT: stp w1, w0, [sp, #8]
+; CHECK-ASM-NEXT: cmp x8, #10
+; CHECK-ASM-NEXT: b.hi .LBB0_5
+; CHECK-ASM-NEXT: // %bb.1: // %entry
+; CHECK-ASM-NEXT: mov w9, #10 // =0xa
+; CHECK-ASM-NEXT: sub x9, x9, x8
+; CHECK-ASM-NEXT: cbz x9, .LBB0_5
+; CHECK-ASM-NEXT: // %bb.2:
+; CHECK-ASM-NEXT: ldrsw x9, [sp, #8]
+; CHECK-ASM-NEXT: adrp x10, B
+; CHECK-ASM-NEXT: add x10, x10, :lo12:B
+; CHECK-ASM-NEXT: strb wzr, [x10, x8]
+; CHECK-ASM-NEXT: cmp x9, #10
+; CHECK-ASM-NEXT: b.hi .LBB0_6
+; CHECK-ASM-NEXT: // %bb.3:
+; CHECK-ASM-NEXT: mov w8, #10 // =0xa
+; CHECK-ASM-NEXT: sub x8, x8, x9
+; CHECK-ASM-NEXT: cbz x8, .LBB0_6
+; CHECK-ASM-NEXT: // %bb.4:
+; CHECK-ASM-NEXT: adrp x8, B2
+; CHECK-ASM-NEXT: add x8, x8, :lo12:B2
+; CHECK-ASM-NEXT: strb wzr, [x8, x9]
+; CHECK-ASM-NEXT: add sp, sp, #16
+; CHECK-ASM-NEXT: .cfi_def_cfa_offset 0
+; CHECK-ASM-NEXT: ret
+; CHECK-ASM-NEXT: .LBB0_5: // %trap
+; CHECK-ASM-NEXT: .cfi_restore_state
+; CHECK-ASM-NEXT: brk #0x1
+; CHECK-ASM-NEXT: .LBB0_6: // %trap3
+; CHECK-ASM-NEXT: brk #0x1
entry:
-; CHECK-ASM: cmp x8, #10
-; CHECK-ASM: b.hi .LBB0_5
-; CHECK-ASM: // %bb.1: // %entry
-; CHECK-ASM: mov w9, #10 // =0xa
-; CHECK-ASM: sub x9, x9, x8
-; CHECK-ASM: cbz x9, .LBB0_5
-; CHECK-ASM: // %bb.2:
-; CHECK-ASM: ldrsw x9, [sp, #8]
-; CHECK-ASM: adrp x10, B
-; CHECK-ASM: add x10, x10, :lo12:B
-; CHECK-ASM: strb wzr, [x10, x8]
-; CHECK-ASM: cmp x9, #10
-; CHECK-ASM: b.hi .LBB0_6
-; CHECK-ASM: // %bb.3:
-; CHECK-ASM: mov w8, #10 // =0xa
-; CHECK-ASM: sub x8, x8, x9
-; CHECK-ASM: cbz x8, .LBB0_6
-; CHECK-ASM: // %bb.4:
-; CHECK-ASM: adrp x8, B2
-; CHECK-ASM: add x8, x8, :lo12:B2
-; CHECK-ASM: strb wzr, [x8, x9]
-; CHECK-ASM: add sp, sp, #16
-; CHECK-ASM: .cfi_def_cfa_offset 0
-; CHECK-ASM: ret
-; CHECK-ASM: .LBB0_5: // %trap
-; CHECK-ASM: .cfi_restore_state
-; CHECK-ASM: brk #0x1
-; CHECK-ASM: .LBB0_6: // %trap3
-; CHECK-ASM: brk #0x1
%i.addr = alloca i32, align 4
%k.addr = alloca i32, align 4
store i32 %i, ptr %i.addr, align 4
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