[llvm] [Mips] Fix inst `sc` disassemble assert when configured -mattr=+ptr64 (PR #158253)

[via llvm-commits]

https://github.com/yingopq updated https://github.com/llvm/llvm-project/pull/158253

>From 5d557be5b052c1cc055fab27194d26828d878267 Mon Sep 17 00:00:00 2001
From: Ying Huang <ying.huang at oss.cipunited.com>
Date: Fri, 12 Sep 2025 04:45:56 -0400
Subject: [PATCH] [Mips] Fix inst `sc` disassemble assert when configured
 -mattr=+ptr64

When mips disassembler process `DecodeMem`, does not consider
Mips::SC64, leading to `Operands.size() = 3`.
And the right `Size` value is 4, when printMemOperand would occur
asserts: `assert(idx < size());`

Fix #157508.
---
 llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 2 +-
 llvm/test/MC/Disassembler/Mips/mips64/sc-ptr64.txt     | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/MC/Disassembler/Mips/mips64/sc-ptr64.txt

diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index b3f6cd1609fbb..cd6ddcf8c14b0 100644
--- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -1468,7 +1468,7 @@ static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address,
   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
-  if (Inst.getOpcode() == Mips::SC ||
+  if (Inst.getOpcode() == Mips::SC || Inst.getOpcode() == Mips::SC64 ||
       Inst.getOpcode() == Mips::SCD)
     Inst.addOperand(MCOperand::createReg(Reg));
 
diff --git a/llvm/test/MC/Disassembler/Mips/mips64/sc-ptr64.txt b/llvm/test/MC/Disassembler/Mips/mips64/sc-ptr64.txt
new file mode 100644
index 0000000000000..3964301b0827e
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Mips/mips64/sc-ptr64.txt
@@ -0,0 +1,3 @@
+# RUN: llvm-mc -triple=mips64el-unknown-linux -disassemble -mattr=+ptr64 -mcpu=mips3 %s | FileCheck %s
+
+0xd8 0x49 0x6f 0xe2 # CHECK: sc $15, 18904($19)