[llvm] [RISCV][CodeGen] Add CodeGen support of Zibi experimental extension (PR #146858)
    Pengcheng Wang via llvm-commits 
    llvm-commits at lists.llvm.org
       
    Sun Sep 14 20:03:20 PDT 2025
    
    
  
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@@ -45,7 +45,8 @@ enum CondCode {
 };
 
 CondCode getOppositeBranchCondition(CondCode);
-unsigned getBrCond(CondCode CC, unsigned SelectOpc = 0);
+unsigned getBrCond(const RISCVSubtarget &STI, CondCode CC,
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wangpc-pp wrote:
Using `SelectCC_GPR_riirr` just like other vendor extension so that we won't have to change this.
https://github.com/llvm/llvm-project/pull/146858
    
    
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