[llvm] [LoongArch][NFC] Add tests for vector type `orn/andn` (PR #158525)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 14 18:53:43 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-loongarch
Author: ZhaoQi (zhaoqi5)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/158525.diff
4 Files Affected:
- (added) llvm/test/CodeGen/LoongArch/lasx/ir-instruction/andn.ll (+78)
- (added) llvm/test/CodeGen/LoongArch/lasx/ir-instruction/orn.ll (+78)
- (added) llvm/test/CodeGen/LoongArch/lsx/ir-instruction/andn.ll (+78)
- (added) llvm/test/CodeGen/LoongArch/lsx/ir-instruction/orn.ll (+78)
``````````diff
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/andn.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/andn.ll
new file mode 100644
index 0000000000000..ea3b6144805ae
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/andn.ll
@@ -0,0 +1,78 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+
+define void @andn_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: andn_v32i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvld $xr1, $a2, 0
+; CHECK-NEXT: xvxori.b $xr0, $xr0, 255
+; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <32 x i8>, ptr %a0
+ %v1 = load <32 x i8>, ptr %a1
+ %v2 = xor <32 x i8> %v0, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+ %v3 = and <32 x i8> %v2, %v1
+ store <32 x i8> %v3, ptr %res
+ ret void
+}
+
+define void @andn_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: andn_v16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvld $xr1, $a2, 0
+; CHECK-NEXT: xvrepli.b $xr2, -1
+; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
+; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <16 x i16>, ptr %a0
+ %v1 = load <16 x i16>, ptr %a1
+ %v2 = xor <16 x i16> %v0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+ %v3 = and <16 x i16> %v2, %v1
+ store <16 x i16> %v3, ptr %res
+ ret void
+}
+
+define void @andn_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: andn_v8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvld $xr1, $a2, 0
+; CHECK-NEXT: xvrepli.b $xr2, -1
+; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
+; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <8 x i32>, ptr %a0
+ %v1 = load <8 x i32>, ptr %a1
+ %v2 = xor <8 x i32> %v0, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
+ %v3 = and <8 x i32> %v2, %v1
+ store <8 x i32> %v3, ptr %res
+ ret void
+}
+
+define void @andn_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: andn_v4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvld $xr1, $a2, 0
+; CHECK-NEXT: xvrepli.b $xr2, -1
+; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
+; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <4 x i64>, ptr %a0
+ %v1 = load <4 x i64>, ptr %a1
+ %v2 = xor <4 x i64> %v0, <i64 -1, i64 -1, i64 -1, i64 -1>
+ %v3 = and <4 x i64> %v2, %v1
+ store <4 x i64> %v3, ptr %res
+ ret void
+}
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/orn.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/orn.ll
new file mode 100644
index 0000000000000..5115fa880271d
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/orn.ll
@@ -0,0 +1,78 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+
+define void @orn_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: orn_v32i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a2, 0
+; CHECK-NEXT: xvld $xr1, $a1, 0
+; CHECK-NEXT: xvxori.b $xr0, $xr0, 255
+; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <32 x i8>, ptr %a0
+ %v1 = load <32 x i8>, ptr %a1
+ %v2 = xor <32 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+ %v3 = or <32 x i8> %v0, %v2
+ store <32 x i8> %v3, ptr %res
+ ret void
+}
+
+define void @orn_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: orn_v16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a2, 0
+; CHECK-NEXT: xvld $xr1, $a1, 0
+; CHECK-NEXT: xvrepli.b $xr2, -1
+; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
+; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <16 x i16>, ptr %a0
+ %v1 = load <16 x i16>, ptr %a1
+ %v2 = xor <16 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+ %v3 = or <16 x i16> %v0, %v2
+ store <16 x i16> %v3, ptr %res
+ ret void
+}
+
+define void @orn_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: orn_v8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a2, 0
+; CHECK-NEXT: xvld $xr1, $a1, 0
+; CHECK-NEXT: xvrepli.b $xr2, -1
+; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
+; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <8 x i32>, ptr %a0
+ %v1 = load <8 x i32>, ptr %a1
+ %v2 = xor <8 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
+ %v3 = or <8 x i32> %v0, %v2
+ store <8 x i32> %v3, ptr %res
+ ret void
+}
+
+define void @orn_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: orn_v4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a2, 0
+; CHECK-NEXT: xvld $xr1, $a1, 0
+; CHECK-NEXT: xvrepli.b $xr2, -1
+; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
+; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <4 x i64>, ptr %a0
+ %v1 = load <4 x i64>, ptr %a1
+ %v2 = xor <4 x i64> %v1, <i64 -1, i64 -1, i64 -1, i64 -1>
+ %v3 = or <4 x i64> %v0, %v2
+ store <4 x i64> %v3, ptr %res
+ ret void
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/andn.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/andn.ll
new file mode 100644
index 0000000000000..4b6a77919659b
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/andn.ll
@@ -0,0 +1,78 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+define void @andn_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: andn_v16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vld $vr1, $a2, 0
+; CHECK-NEXT: vxori.b $vr0, $vr0, 255
+; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <16 x i8>, ptr %a0
+ %v1 = load <16 x i8>, ptr %a1
+ %v2 = xor <16 x i8> %v0, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+ %v3 = and <16 x i8> %v2, %v1
+ store <16 x i8> %v3, ptr %res
+ ret void
+}
+
+define void @andn_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: andn_v8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vld $vr1, $a2, 0
+; CHECK-NEXT: vrepli.b $vr2, -1
+; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
+; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <8 x i16>, ptr %a0
+ %v1 = load <8 x i16>, ptr %a1
+ %v2 = xor <8 x i16> %v0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+ %v3 = and <8 x i16> %v2, %v1
+ store <8 x i16> %v3, ptr %res
+ ret void
+}
+
+define void @andn_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: andn_v4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vld $vr1, $a2, 0
+; CHECK-NEXT: vrepli.b $vr2, -1
+; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
+; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <4 x i32>, ptr %a0
+ %v1 = load <4 x i32>, ptr %a1
+ %v2 = xor <4 x i32> %v0, <i32 -1, i32 -1, i32 -1, i32 -1>
+ %v3 = and <4 x i32> %v2, %v1
+ store <4 x i32> %v3, ptr %res
+ ret void
+}
+
+define void @andn_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: andn_v2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vld $vr1, $a2, 0
+; CHECK-NEXT: vrepli.b $vr2, -1
+; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
+; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <2 x i64>, ptr %a0
+ %v1 = load <2 x i64>, ptr %a1
+ %v2 = xor <2 x i64> %v0, <i64 -1, i64 -1>
+ %v3 = and <2 x i64> %v2, %v1
+ store <2 x i64> %v3, ptr %res
+ ret void
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/orn.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/orn.ll
new file mode 100644
index 0000000000000..524dfd616fa3b
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/orn.ll
@@ -0,0 +1,78 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+define void @orn_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: orn_v16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a2, 0
+; CHECK-NEXT: vld $vr1, $a1, 0
+; CHECK-NEXT: vxori.b $vr0, $vr0, 255
+; CHECK-NEXT: vor.v $vr0, $vr1, $vr0
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <16 x i8>, ptr %a0
+ %v1 = load <16 x i8>, ptr %a1
+ %v2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+ %v3 = or <16 x i8> %v0, %v2
+ store <16 x i8> %v3, ptr %res
+ ret void
+}
+
+define void @orn_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: orn_v8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a2, 0
+; CHECK-NEXT: vld $vr1, $a1, 0
+; CHECK-NEXT: vrepli.b $vr2, -1
+; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
+; CHECK-NEXT: vor.v $vr0, $vr1, $vr0
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <8 x i16>, ptr %a0
+ %v1 = load <8 x i16>, ptr %a1
+ %v2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+ %v3 = or <8 x i16> %v0, %v2
+ store <8 x i16> %v3, ptr %res
+ ret void
+}
+
+define void @orn_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: orn_v4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a2, 0
+; CHECK-NEXT: vld $vr1, $a1, 0
+; CHECK-NEXT: vrepli.b $vr2, -1
+; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
+; CHECK-NEXT: vor.v $vr0, $vr1, $vr0
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <4 x i32>, ptr %a0
+ %v1 = load <4 x i32>, ptr %a1
+ %v2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
+ %v3 = or <4 x i32> %v0, %v2
+ store <4 x i32> %v3, ptr %res
+ ret void
+}
+
+define void @orn_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: orn_v2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a2, 0
+; CHECK-NEXT: vld $vr1, $a1, 0
+; CHECK-NEXT: vrepli.b $vr2, -1
+; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
+; CHECK-NEXT: vor.v $vr0, $vr1, $vr0
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <2 x i64>, ptr %a0
+ %v1 = load <2 x i64>, ptr %a1
+ %v2 = xor <2 x i64> %v1, <i64 -1, i64 -1>
+ %v3 = or <2 x i64> %v0, %v2
+ store <2 x i64> %v3, ptr %res
+ ret void
+}
``````````
</details>
https://github.com/llvm/llvm-project/pull/158525
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