[llvm] unpack packed instructions overlapped by MFMAs post-RA scheduling (PR #157968)

[Jeffrey Byrnes via llvm-commits]

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@@ -417,6 +460,261 @@ bool SIPreEmitPeephole::removeExeczBranch(MachineInstr &MI,
   return true;
 }
 
+bool SIPreEmitPeephole::isUnpackingSupportedInstr(MachineInstr &MI) const {
+  unsigned Opcode = MI.getOpcode();
+  switch (Opcode) {
+  case AMDGPU::V_PK_ADD_F32:
+  case AMDGPU::V_PK_MUL_F32:
+  case AMDGPU::V_PK_FMA_F32:
+    return true;
+  default:
+    return false;
+  }
+  llvm_unreachable("Fully covered switch");
+}
+
+bool SIPreEmitPeephole::hasRWDependencies(const MachineInstr &PredMI,
+                                          const MachineInstr &SuccMI) {
+  for (const MachineOperand &PredOps : PredMI.operands()) {
+    if (!PredOps.isReg() || !PredOps.isDef())
+      continue;
+    Register PredReg = PredOps.getReg();
+    if (!PredReg.isValid())
+      continue;
+    for (const MachineOperand &SuccOps : SuccMI.operands()) {
+      if (!SuccOps.isReg())
+        continue;
+      Register SuccReg = SuccOps.getReg();
+      if (!SuccReg.isValid())
+        continue;
+      if ((PredReg == SuccReg) || TRI->regsOverlap(PredReg, SuccReg))
+        return true;
+    }
+  }
+  return false;
+}
+
+bool SIPreEmitPeephole::canUnpackingIntroduceDependencies(
+    const MachineInstr &MI) {
+  unsigned OpCode = MI.getOpcode();
+  bool IsFMA = OpCode == AMDGPU::V_PK_FMA_F32;
+  MachineOperand DstMO = MI.getOperand(0);
+  Register DstReg = DstMO.getReg();
+  Register SrcReg0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0)->getReg();
+  Register SrcReg1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1)->getReg();
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jrbyrnes wrote:

Please add tests where src0/src1 operands are immediates.

https://github.com/llvm/llvm-project/pull/157968