[llvm] [LLVM][AArch64] Optimize sign bit tests with TST instruction for SIGN_EXTEND patterns (PR #158061)

[guan jian via llvm-commits]

================
@@ -11630,6 +11630,48 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(
       return DAG.getNode(ISD::AND, DL, VT, LHS, Shift);
     }
 
+    // Check for sign bit test patterns that can use TST optimization.
+    // (SELECT_CC setlt, singn_extend_inreg, 0, tval, fval)
+    //                          -> TST %operand, sign_bit; CSEL
+    // (SELECT_CC setlt, singn_extend, 0, tval, fval)
+    //                          -> TST %operand, sign_bit; CSEL
----------------
rez5427 wrote:

I found a case would trigger this:
```
int test_sign_extend(short x) {
    if (x < 0) {
      return 42;
  } else {
      return 17;
  }
}
···
clang generates this:
```
	mov	w8, #17                         // =0x11
	tst	w0, #0x8000
	mov	w9, #42                         // =0x2a
	csel	w0, w9, w8, ne
	ret
```
original clang generates:
```
        sxth    w9, w0
        mov     w8, #17                         // =0x11
        cmp     w9, #0
        mov     w9, #42                         // =0x2a
        csel    w0, w9, w8, mi
        ret
```

https://github.com/llvm/llvm-project/pull/158061