[llvm] [AMDGPU] Support lowering of cluster related instrinsics (PR #157978)

[Matt Arsenault via llvm-commits]

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@@ -7415,6 +7552,22 @@ bool AMDGPULegalizerInfo::legalizeWaveID(MachineInstr &MI,
   return true;
 }
 
+bool AMDGPULegalizerInfo::legalizeConstHwRegRead(MachineInstr &MI,
+                                                 MachineIRBuilder &B,
+                                                 AMDGPU::Hwreg::Id HwReg,
+                                                 unsigned LowBit,
+                                                 unsigned Width) const {
+  MachineRegisterInfo &MRI = *B.getMRI();
+  Register DstReg = MI.getOperand(0).getReg();
+  if (!MRI.getRegClassOrNull(DstReg))
+    MRI.setRegClass(DstReg, &AMDGPU::SReg_32RegClass);
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arsenm wrote:

constrainSelectedInstRegOperands, or constrainGenericRegister if you really want to micro-optimize and handle the one operand 

https://github.com/llvm/llvm-project/pull/157978