[llvm] f32874f - [LegalizeIntegerTypes] Use getShiftAmountConstant.

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 12 16:15:05 PDT 2025


Author: Craig Topper
Date: 2025-09-12T16:10:01-07:00
New Revision: f32874f77b5a6065a705ffc35b48bff1545cd6cd

URL: https://github.com/llvm/llvm-project/commit/f32874f77b5a6065a705ffc35b48bff1545cd6cd
DIFF: https://github.com/llvm/llvm-project/commit/f32874f77b5a6065a705ffc35b48bff1545cd6cd.diff

LOG: [LegalizeIntegerTypes] Use getShiftAmountConstant.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 9e85f08abb766..87570e6f44a6f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -5254,9 +5254,9 @@ void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
     SDValue MulLo, MulHi;
     TLI.forceExpandWideMUL(DAG, dl, /*Signed=*/true, N->getOperand(0),
                            N->getOperand(1), MulLo, MulHi);
-    SDValue SRA =
-        DAG.getNode(ISD::SRA, dl, VT, MulLo,
-                    DAG.getConstant(VT.getScalarSizeInBits() - 1, dl, VT));
+    SDValue SRA = DAG.getNode(
+        ISD::SRA, dl, VT, MulLo,
+        DAG.getShiftAmountConstant(VT.getScalarSizeInBits() - 1, VT, dl));
     SDValue Overflow =
         DAG.getSetCC(dl, N->getValueType(1), MulHi, SRA, ISD::SETNE);
     SplitInteger(MulLo, Lo, Hi);


        


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