[llvm] [LLVM][AArch64] Optimize sign bit tests with TST instruction for SIGN_EXTEND patterns (PR #158061)

Eli Friedman via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 12 12:47:04 PDT 2025


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@@ -11630,6 +11630,48 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(
       return DAG.getNode(ISD::AND, DL, VT, LHS, Shift);
     }
 
+    // Check for sign bit test patterns that can use TST optimization.
+    // (SELECT_CC setlt, singn_extend_inreg, 0, tval, fval)
+    //                          -> TST %operand, sign_bit; CSEL
+    // (SELECT_CC setlt, singn_extend, 0, tval, fval)
+    //                          -> TST %operand, sign_bit; CSEL
----------------
efriedma-quic wrote:

This seems like it should also apply to comparisons that feed into a branch.

Do you have an example of C code that triggers this? In practice it seems like instcombine transforms a lot of the cases where this transform would actually be useful.

https://github.com/llvm/llvm-project/pull/158061


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