[llvm] [AArch64] Add ISel support for partial reductions to use SVE2.1 udot/sdot (PR #158310)

[Sander de Smalen via llvm-commits]

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@@ -0,0 +1,62 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 < %s | FileCheck %s
+
+define <vscale x 4 x i32> @udot(<vscale x 4 x i32> %acc, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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sdesmalen-arm wrote:

Can we also have some tests for wider SVE vectors where vscale_range is larger than 1?
(see for example #142032 and `llvm/test/CodeGen/AArch64/sve-fixed-length-partial-reduce.ll`)

https://github.com/llvm/llvm-project/pull/158310