[llvm] [AArch64][GlobalISel] Add codegen for simd fpcvt intrinsics (PR #157680)

[David Green via llvm-commits]

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@@ -5232,19 +5232,54 @@ defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;
 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
 
+defm FCVTAS : SIMDFPTwoScalarFCVT<   0, 0, 0b11100, "fcvtas", int_aarch64_neon_fcvtas>;
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davemgreen wrote:

It's just that I was considering the v1i32 instructions "scalar neon instructions" that are really operating on the first lane of a neon register and require hasNeon I believe. The SDr style instructions are "FP" instructions that tend to operate between FPR and GPR. I would still consider the v1i32 instructions "Advanced SIMD two scalar instructions" and a little different to normal fp instructions.

https://github.com/llvm/llvm-project/pull/157680