[llvm] CodeGen: Remove MachineFunction argument from getPointerRegClass (PR #158185)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 12 01:47:28 PDT 2025
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/158185
>From 27e24b96a353f5e3461afd488aff08c6e14830c4 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 11 Sep 2025 18:39:58 +0900
Subject: [PATCH 1/2] CodeGen: Remove MachineFunction argument from
getPointerRegClass
getPointerRegClass is a layering violation. Its primary purpose
is to determine how to interpret an MCInstrDesc's operands RegClass
fields. This should be context free, and only depend on the subtarget.
The model of this is also wrong, since this should be an
instruction / operand specific property, not a global pointer class.
Remove the the function argument to help stage removal of this hook
and avoid introducing any new obstacles to replacing it.
The remaining uses of the function were to get the subtarget, which
TargetRegisterInfo already belongs to. A few targets needed new
subtarget derived properties copied there.
---
llvm/include/llvm/CodeGen/TargetRegisterInfo.h | 2 +-
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 +-
llvm/lib/CodeGen/MachineInstr.cpp | 2 +-
llvm/lib/CodeGen/TargetInstrInfo.cpp | 2 +-
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 2 +-
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 3 +--
llvm/lib/Target/AArch64/AArch64RegisterInfo.h | 3 +--
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 4 ++--
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | 3 +--
llvm/lib/Target/ARM/ARMBaseRegisterInfo.h | 3 +--
llvm/lib/Target/ARM/Thumb1InstrInfo.cpp | 2 +-
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 2 +-
llvm/lib/Target/ARM/ThumbRegisterInfo.cpp | 12 ++++++------
llvm/lib/Target/ARM/ThumbRegisterInfo.h | 8 +++++---
llvm/lib/Target/AVR/AVRRegisterInfo.cpp | 3 +--
llvm/lib/Target/AVR/AVRRegisterInfo.h | 3 +--
llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp | 3 +--
llvm/lib/Target/Hexagon/HexagonRegisterInfo.h | 3 +--
llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h | 3 +--
llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp | 3 +--
llvm/lib/Target/MSP430/MSP430RegisterInfo.h | 5 ++---
llvm/lib/Target/Mips/Mips16InstrInfo.cpp | 2 +-
llvm/lib/Target/Mips/Mips16RegisterInfo.cpp | 3 ++-
llvm/lib/Target/Mips/Mips16RegisterInfo.h | 3 +--
llvm/lib/Target/Mips/MipsRegisterInfo.cpp | 13 ++++++-------
llvm/lib/Target/Mips/MipsRegisterInfo.h | 8 +++++---
llvm/lib/Target/Mips/MipsSEInstrInfo.cpp | 2 +-
llvm/lib/Target/Mips/MipsSERegisterInfo.cpp | 3 ++-
llvm/lib/Target/Mips/MipsSERegisterInfo.h | 2 +-
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 2 +-
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 5 ++---
llvm/lib/Target/PowerPC/PPCRegisterInfo.h | 2 +-
llvm/lib/Target/RISCV/RISCVRegisterInfo.h | 3 +--
llvm/lib/Target/Sparc/SparcInstrInfo.cpp | 2 +-
llvm/lib/Target/Sparc/SparcRegisterInfo.cpp | 12 ++++++------
llvm/lib/Target/Sparc/SparcRegisterInfo.h | 11 ++++++++---
llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 2 +-
llvm/lib/Target/SystemZ/SystemZRegisterInfo.h | 3 +--
llvm/lib/Target/VE/VERegisterInfo.cpp | 3 +--
llvm/lib/Target/VE/VERegisterInfo.h | 3 +--
.../Target/WebAssembly/WebAssemblyFrameLowering.cpp | 4 ++--
.../Target/WebAssembly/WebAssemblyRegisterInfo.cpp | 10 ++++------
.../Target/WebAssembly/WebAssemblyRegisterInfo.h | 3 +--
llvm/lib/Target/X86/X86RegisterInfo.cpp | 13 ++++++-------
llvm/lib/Target/X86/X86RegisterInfo.h | 6 ++++--
46 files changed, 94 insertions(+), 103 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 73ccc8ed5b11d..3f576b2007137 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -883,7 +883,7 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
/// If a target supports multiple different pointer register classes,
/// kind specifies which one is indicated.
virtual const TargetRegisterClass *
- getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
+ getPointerRegClass(unsigned Kind = 0) const {
llvm_unreachable("Target didn't implement getPointerRegClass!");
}
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 541269ab6bfce..768e3713f78e2 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1863,7 +1863,7 @@ bool IRTranslator::translateVectorDeinterleave2Intrinsic(
void IRTranslator::getStackGuard(Register DstReg,
MachineIRBuilder &MIRBuilder) {
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
- MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF));
+ MRI->setRegClass(DstReg, TRI->getPointerRegClass());
auto MIB =
MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD, {DstReg}, {});
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 79047f732808a..55ec049453607 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1003,7 +1003,7 @@ MachineInstr::getRegClassConstraint(unsigned OpIdx,
// Assume that all registers in a memory operand are pointers.
if (F.isMemKind())
- return TRI->getPointerRegClass(MF);
+ return TRI->getPointerRegClass();
return nullptr;
}
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 0d7b128fc736e..f0da03b876d6a 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -67,7 +67,7 @@ TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
short RegClass = MCID.operands()[OpNum].RegClass;
if (MCID.operands()[OpNum].isLookupPtrRegClass())
- return TRI->getPointerRegClass(MF, RegClass);
+ return TRI->getPointerRegClass(RegClass);
// Instructions like INSERT_SUBREG do not have fixed register classes.
if (RegClass < 0)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 6fdc981fc21a5..10671f09551a4 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -574,7 +574,7 @@ bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
// We need to make sure that this one operand does not end up in XZR, thus
// require the address to be in a PointerRegClass register.
const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
- const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF);
+ const TargetRegisterClass *TRC = TRI->getPointerRegClass();
SDLoc dl(Op);
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64);
SDValue NewOp =
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 77dfab83a834a..8d167b56e6ca3 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -610,8 +610,7 @@ bool AArch64RegisterInfo::isAsmClobberable(const MachineFunction &MF,
}
const TargetRegisterClass *
-AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
- unsigned Kind) const {
+AArch64RegisterInfo::getPointerRegClass(unsigned Kind) const {
return &AArch64::GPR64spRegClass;
}
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
index 1ed8e959fdd2d..72a7676241770 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
@@ -102,8 +102,7 @@ class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
bool isAsmClobberable(const MachineFunction &MF,
MCRegister PhysReg) const override;
const TargetRegisterClass *
- getPointerRegClass(const MachineFunction &MF,
- unsigned Kind = 0) const override;
+ getPointerRegClass(unsigned Kind = 0) const override;
const TargetRegisterClass *
getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 22488384759be..205237fefe785 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1108,8 +1108,8 @@ bool SIRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
SIInstrFlags::FlatScratch);
}
-const TargetRegisterClass *SIRegisterInfo::getPointerRegClass(
- const MachineFunction &MF, unsigned Kind) const {
+const TargetRegisterClass *
+SIRegisterInfo::getPointerRegClass(unsigned Kind) const {
// This is inaccurate. It depends on the instruction and address space. The
// only place where we should hit this is for dealing with frame indexes /
// private accesses, so this is correct in that case.
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index eeefef1116aa3..7b91ba7bc581f 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -154,8 +154,8 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
int64_t Offset) const override;
- const TargetRegisterClass *getPointerRegClass(
- const MachineFunction &MF, unsigned Kind = 0) const override;
+ const TargetRegisterClass *
+ getPointerRegClass(unsigned Kind = 0) const override;
/// Returns a legal register class to copy a register in the specified class
/// to or from. If it is possible to copy the register directly without using
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index bc20daf0cfbbc..0d4ecaec1c23e 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -310,8 +310,7 @@ ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
}
const TargetRegisterClass *
-ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
- const {
+ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
return &ARM::GPRRegClass;
}
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
index 69e10ac2a54d2..5b67b34089d7e 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
@@ -91,8 +91,7 @@ class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
MCRegister PhysReg) const override;
const TargetRegisterClass *
- getPointerRegClass(const MachineFunction &MF,
- unsigned Kind = 0) const override;
+ getPointerRegClass(unsigned Kind = 0) const override;
const TargetRegisterClass *
getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index ce4ee157289df..4b8c2fd569ead 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -24,7 +24,7 @@
using namespace llvm;
Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
- : ARMBaseInstrInfo(STI) {}
+ : ARMBaseInstrInfo(STI), RI(STI) {}
/// Return the noop instruction to use for a noop.
MCInst Thumb1InstrInfo::getNop() const {
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index e91441b12fe6f..9dd0e430a0ea1 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -46,7 +46,7 @@ PreferNoCSEL("prefer-no-csel", cl::Hidden,
cl::init(false));
Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
- : ARMBaseInstrInfo(STI) {}
+ : ARMBaseInstrInfo(STI), RI(STI) {}
/// Return the noop instruction to use for a noop.
MCInst Thumb2InstrInfo::getNop() const {
diff --git a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
index 911502605c227..12875c233312a 100644
--- a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
@@ -35,12 +35,13 @@ extern cl::opt<bool> ReuseFrameIndexVals;
using namespace llvm;
-ThumbRegisterInfo::ThumbRegisterInfo() = default;
+ThumbRegisterInfo::ThumbRegisterInfo(const ARMSubtarget &STI)
+ : IsThumb1Only(STI.isThumb1Only()) {}
const TargetRegisterClass *
ThumbRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
const MachineFunction &MF) const {
- if (!MF.getSubtarget<ARMSubtarget>().isThumb1Only())
+ if (!IsThumb1Only)
return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC, MF);
if (ARM::tGPRRegClass.hasSubClassEq(RC))
@@ -49,10 +50,9 @@ ThumbRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
}
const TargetRegisterClass *
-ThumbRegisterInfo::getPointerRegClass(const MachineFunction &MF,
- unsigned Kind) const {
- if (!MF.getSubtarget<ARMSubtarget>().isThumb1Only())
- return ARMBaseRegisterInfo::getPointerRegClass(MF, Kind);
+ThumbRegisterInfo::getPointerRegClass(unsigned Kind) const {
+ if (!IsThumb1Only)
+ return ARMBaseRegisterInfo::getPointerRegClass(Kind);
return &ARM::tGPRRegClass;
}
diff --git a/llvm/lib/Target/ARM/ThumbRegisterInfo.h b/llvm/lib/Target/ARM/ThumbRegisterInfo.h
index ccfe211b808a5..b077d302297ca 100644
--- a/llvm/lib/Target/ARM/ThumbRegisterInfo.h
+++ b/llvm/lib/Target/ARM/ThumbRegisterInfo.h
@@ -23,16 +23,18 @@ namespace llvm {
class ARMBaseInstrInfo;
struct ThumbRegisterInfo : public ARMBaseRegisterInfo {
+private:
+ const bool IsThumb1Only;
+
public:
- ThumbRegisterInfo();
+ ThumbRegisterInfo(const ARMSubtarget &STI);
const TargetRegisterClass *
getLargestLegalSuperClass(const TargetRegisterClass *RC,
const MachineFunction &MF) const override;
const TargetRegisterClass *
- getPointerRegClass(const MachineFunction &MF,
- unsigned Kind = 0) const override;
+ getPointerRegClass(unsigned Kind = 0) const override;
/// emitLoadConstPool - Emits a load from constpool to materialize the
/// specified immediate.
diff --git a/llvm/lib/Target/AVR/AVRRegisterInfo.cpp b/llvm/lib/Target/AVR/AVRRegisterInfo.cpp
index 051affe7110dd..18bea848baeab 100644
--- a/llvm/lib/Target/AVR/AVRRegisterInfo.cpp
+++ b/llvm/lib/Target/AVR/AVRRegisterInfo.cpp
@@ -289,8 +289,7 @@ Register AVRRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
}
const TargetRegisterClass *
-AVRRegisterInfo::getPointerRegClass(const MachineFunction &MF,
- unsigned Kind) const {
+AVRRegisterInfo::getPointerRegClass(unsigned Kind) const {
// FIXME: Currently we're using avr-gcc as reference, so we restrict
// ptrs to Y and Z regs. Though avr-gcc has buggy implementation
// of memory constraint, so we can fix it and bit avr-gcc here ;-)
diff --git a/llvm/lib/Target/AVR/AVRRegisterInfo.h b/llvm/lib/Target/AVR/AVRRegisterInfo.h
index 8eb0cf3039bbd..e69696b4d9160 100644
--- a/llvm/lib/Target/AVR/AVRRegisterInfo.h
+++ b/llvm/lib/Target/AVR/AVRRegisterInfo.h
@@ -44,8 +44,7 @@ class AVRRegisterInfo : public AVRGenRegisterInfo {
Register getFrameRegister(const MachineFunction &MF) const override;
const TargetRegisterClass *
- getPointerRegClass(const MachineFunction &MF,
- unsigned Kind = 0) const override;
+ getPointerRegClass(unsigned Kind = 0) const override;
/// Splits a 16-bit `DREGS` register into the lo/hi register pair.
/// \param Reg A 16-bit register to split.
diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
index 2731c523963e5..77ce983d24785 100644
--- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
@@ -444,7 +444,6 @@ bool HexagonRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF)
}
const TargetRegisterClass *
-HexagonRegisterInfo::getPointerRegClass(const MachineFunction &MF,
- unsigned Kind) const {
+HexagonRegisterInfo::getPointerRegClass(unsigned Kind) const {
return &Hexagon::IntRegsRegClass;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h
index 72153980236e9..945b8608cd948 100644
--- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h
@@ -72,8 +72,7 @@ class HexagonRegisterInfo : public HexagonGenRegisterInfo {
const TargetRegisterClass *RC) const;
const TargetRegisterClass *
- getPointerRegClass(const MachineFunction &MF,
- unsigned Kind = 0) const override;
+ getPointerRegClass(unsigned Kind = 0) const override;
bool isEHReturnCalleeSaveReg(Register Reg) const;
};
diff --git a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h
index d1e40254c2972..53381c28898b8 100644
--- a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h
+++ b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h
@@ -33,8 +33,7 @@ struct LoongArchRegisterInfo : public LoongArchGenRegisterInfo {
BitVector getReservedRegs(const MachineFunction &MF) const override;
const TargetRegisterClass *
- getPointerRegClass(const MachineFunction &MF,
- unsigned Kind = 0) const override {
+ getPointerRegClass(unsigned Kind = 0) const override {
return &LoongArch::GPRRegClass;
}
diff --git a/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp b/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp
index 44596a1527a2d..c1a1e8e83e0d3 100644
--- a/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp
+++ b/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp
@@ -91,8 +91,7 @@ BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
}
const TargetRegisterClass *
-MSP430RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
- const {
+MSP430RegisterInfo::getPointerRegClass(unsigned Kind) const {
return &MSP430::GR16RegClass;
}
diff --git a/llvm/lib/Target/MSP430/MSP430RegisterInfo.h b/llvm/lib/Target/MSP430/MSP430RegisterInfo.h
index 51e07f4e8e9ea..fbca97361232d 100644
--- a/llvm/lib/Target/MSP430/MSP430RegisterInfo.h
+++ b/llvm/lib/Target/MSP430/MSP430RegisterInfo.h
@@ -28,9 +28,8 @@ class MSP430RegisterInfo : public MSP430GenRegisterInfo {
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
BitVector getReservedRegs(const MachineFunction &MF) const override;
- const TargetRegisterClass*
- getPointerRegClass(const MachineFunction &MF,
- unsigned Kind = 0) const override;
+ const TargetRegisterClass *
+ getPointerRegClass(unsigned Kind = 0) const override;
bool eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
index cafc11b8a0d9b..5d08f560c3c36 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -37,7 +37,7 @@ using namespace llvm;
#define DEBUG_TYPE "mips16-instrinfo"
Mips16InstrInfo::Mips16InstrInfo(const MipsSubtarget &STI)
- : MipsInstrInfo(STI, Mips::Bimm16) {}
+ : MipsInstrInfo(STI, Mips::Bimm16), RI(STI) {}
const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
return RI;
diff --git a/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp b/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
index d257f02b2bc6f..66099593b6311 100644
--- a/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
@@ -28,7 +28,8 @@ using namespace llvm;
#define DEBUG_TYPE "mips16-registerinfo"
-Mips16RegisterInfo::Mips16RegisterInfo() = default;
+Mips16RegisterInfo::Mips16RegisterInfo(const MipsSubtarget &STI)
+ : MipsRegisterInfo(STI) {}
bool Mips16RegisterInfo::requiresRegisterScavenging
(const MachineFunction &MF) const {
diff --git a/llvm/lib/Target/Mips/Mips16RegisterInfo.h b/llvm/lib/Target/Mips/Mips16RegisterInfo.h
index ff115b30162b9..d0954ccba5912 100644
--- a/llvm/lib/Target/Mips/Mips16RegisterInfo.h
+++ b/llvm/lib/Target/Mips/Mips16RegisterInfo.h
@@ -16,10 +16,9 @@
#include "MipsRegisterInfo.h"
namespace llvm {
-
class Mips16RegisterInfo : public MipsRegisterInfo {
public:
- Mips16RegisterInfo();
+ Mips16RegisterInfo(const MipsSubtarget &STI);
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
index 539288e8da592..4d105bddd4d9c 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -37,27 +37,26 @@ using namespace llvm;
#define GET_REGINFO_TARGET_DESC
#include "MipsGenRegisterInfo.inc"
-MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {
+MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &STI)
+ : MipsGenRegisterInfo(Mips::RA), ArePtrs64bit(STI.getABI().ArePtrs64bit()) {
MIPS_MC::initLLVMToCVRegMapping(this);
}
unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
const TargetRegisterClass *
-MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
- unsigned Kind) const {
- MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
+MipsRegisterInfo::getPointerRegClass(unsigned Kind) const {
MipsPtrClass PtrClassKind = static_cast<MipsPtrClass>(Kind);
switch (PtrClassKind) {
case MipsPtrClass::Default:
- return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
+ return ArePtrs64bit ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
case MipsPtrClass::GPR16MM:
return &Mips::GPRMM16RegClass;
case MipsPtrClass::StackPointer:
- return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass;
+ return ArePtrs64bit ? &Mips::SP64RegClass : &Mips::SP32RegClass;
case MipsPtrClass::GlobalPointer:
- return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass;
+ return ArePtrs64bit ? &Mips::GP64RegClass : &Mips::GP32RegClass;
}
llvm_unreachable("Unknown pointer kind");
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.h b/llvm/lib/Target/Mips/MipsRegisterInfo.h
index b002f4cf3ae7a..296ea82f99d7d 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.h
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.h
@@ -25,6 +25,9 @@ namespace llvm {
class TargetRegisterClass;
class MipsRegisterInfo : public MipsGenRegisterInfo {
+private:
+ const bool ArePtrs64bit;
+
public:
enum class MipsPtrClass {
/// The default register class for integer values.
@@ -38,14 +41,13 @@ class MipsRegisterInfo : public MipsGenRegisterInfo {
GlobalPointer = 3,
};
- MipsRegisterInfo();
+ MipsRegisterInfo(const MipsSubtarget &STI);
/// Get PIC indirect call register
static unsigned getPICCallReg();
/// Code Generation virtual methods...
- const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
- unsigned Kind) const override;
+ const TargetRegisterClass *getPointerRegClass(unsigned Kind) const override;
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const override;
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
index caa20f72aacf9..9f00369d8998a 100644
--- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -28,7 +28,7 @@ static unsigned getUnconditionalBranch(const MipsSubtarget &STI) {
}
MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI)
- : MipsInstrInfo(STI, getUnconditionalBranch(STI)), RI() {}
+ : MipsInstrInfo(STI, getUnconditionalBranch(STI)), RI(STI) {}
const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
return RI;
diff --git a/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp b/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
index feb2b3d2010b4..1326878f7e17e 100644
--- a/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
@@ -34,7 +34,8 @@ using namespace llvm;
#define DEBUG_TYPE "mips-reg-info"
-MipsSERegisterInfo::MipsSERegisterInfo() = default;
+MipsSERegisterInfo::MipsSERegisterInfo(const MipsSubtarget &STI)
+ : MipsRegisterInfo(STI) {}
bool MipsSERegisterInfo::
requiresRegisterScavenging(const MachineFunction &MF) const {
diff --git a/llvm/lib/Target/Mips/MipsSERegisterInfo.h b/llvm/lib/Target/Mips/MipsSERegisterInfo.h
index cc8496e0268be..5de20c4a8f111 100644
--- a/llvm/lib/Target/Mips/MipsSERegisterInfo.h
+++ b/llvm/lib/Target/Mips/MipsSERegisterInfo.h
@@ -20,7 +20,7 @@ namespace llvm {
class MipsSERegisterInfo : public MipsRegisterInfo {
public:
- MipsSERegisterInfo();
+ MipsSERegisterInfo(const MipsSubtarget &STI);
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 415164fc9e2cb..89165fa8f8fdb 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -401,7 +401,7 @@ namespace {
// We need to make sure that this one operand does not end up in r0
// (because we might end up lowering this as 0(%op)).
const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
- const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
+ const TargetRegisterClass *TRC = TRI->getPointerRegClass(/*Kind=*/1);
SDLoc dl(Op);
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
SDValue NewOp =
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index f1230407b1649..366bc73ac52f3 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -164,8 +164,7 @@ PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes.
const TargetRegisterClass *
-PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
- const {
+PPCRegisterInfo::getPointerRegClass(unsigned Kind) const {
// Note that PPCInstrInfo::foldImmediate also directly uses this Kind value
// when it checks for ZERO folding.
if (Kind == 1) {
@@ -2022,7 +2021,7 @@ Register PPCRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
const MCInstrDesc &MCID = TII.get(ADDriOpc);
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
- const TargetRegisterClass *RC = getPointerRegClass(MF);
+ const TargetRegisterClass *RC = getPointerRegClass();
Register BaseReg = MRI.createVirtualRegister(RC);
MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
index 849f856b5419e..560690208f704 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -79,7 +79,7 @@ class PPCRegisterInfo : public PPCGenRegisterInfo {
/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes.
const TargetRegisterClass *
- getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
+ getPointerRegClass(unsigned Kind = 0) const override;
const TargetRegisterClass *
getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index 2810139bf52ea..67726db504122 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -123,8 +123,7 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
}
const TargetRegisterClass *
- getPointerRegClass(const MachineFunction &MF,
- unsigned Kind = 0) const override {
+ getPointerRegClass(unsigned Kind = 0) const override {
return &RISCV::GPRRegClass;
}
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
index cd0f649912980..e28f4457263f4 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -38,7 +38,7 @@ static cl::opt<unsigned>
void SparcInstrInfo::anchor() {}
SparcInstrInfo::SparcInstrInfo(const SparcSubtarget &ST)
- : SparcGenInstrInfo(ST, SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(),
+ : SparcGenInstrInfo(ST, SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(ST),
Subtarget(ST) {}
/// isLoadFromStackSlot - If the specified machine instruction is a direct
diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
index e4db27a63076d..0a14746f587bb 100644
--- a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -31,7 +31,8 @@ static cl::opt<bool>
ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
cl::desc("Reserve application registers (%g2-%g4)"));
-SparcRegisterInfo::SparcRegisterInfo() : SparcGenRegisterInfo(SP::O7) {}
+SparcRegisterInfo::SparcRegisterInfo(const SparcSubtarget &STI)
+ : SparcGenRegisterInfo(SP::O7), Is64Bit(STI.is64Bit()) {}
const MCPhysReg*
SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
@@ -111,11 +112,10 @@ bool SparcRegisterInfo::isReservedReg(const MachineFunction &MF,
return getReservedRegs(MF)[Reg];
}
-const TargetRegisterClass*
-SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
- unsigned Kind) const {
- const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
- return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
+const TargetRegisterClass *
+SparcRegisterInfo::getPointerRegClass(unsigned Kind) const {
+ assert(Kind == 0 && "this should only be used for default cases");
+ return Is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
}
static void replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II,
diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.h b/llvm/lib/Target/Sparc/SparcRegisterInfo.h
index eae859ce1a519..0e9966d6f44b0 100644
--- a/llvm/lib/Target/Sparc/SparcRegisterInfo.h
+++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.h
@@ -19,8 +19,14 @@
#include "SparcGenRegisterInfo.inc"
namespace llvm {
+class SparcSubtarget;
+
struct SparcRegisterInfo : public SparcGenRegisterInfo {
- SparcRegisterInfo();
+private:
+ const bool Is64Bit;
+
+public:
+ SparcRegisterInfo(const SparcSubtarget &STI);
/// Code Generation virtual methods...
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
@@ -32,8 +38,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
BitVector getReservedRegs(const MachineFunction &MF) const override;
bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const;
- const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
- unsigned Kind) const override;
+ const TargetRegisterClass *getPointerRegClass(unsigned Kind) const override;
bool eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index 6f146b67f8566..a05fdc74e6366 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -1851,7 +1851,7 @@ bool SystemZDAGToDAGISel::SelectInlineAsmMemoryOperand(
if (selectBDXAddr(Form, DispRange, Op, Base, Disp, Index)) {
const TargetRegisterClass *TRC =
- Subtarget->getRegisterInfo()->getPointerRegClass(*MF);
+ Subtarget->getRegisterInfo()->getPointerRegClass();
SDLoc DL(Base);
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), DL, MVT::i32);
diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
index 460be432811a4..b1de145db3d31 100644
--- a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
@@ -135,8 +135,7 @@ struct SystemZRegisterInfo : public SystemZGenRegisterInfo {
/// This is currently only used by LOAD_STACK_GUARD, which requires a non-%r0
/// register, hence ADDR64.
const TargetRegisterClass *
- getPointerRegClass(const MachineFunction &MF,
- unsigned Kind=0) const override {
+ getPointerRegClass(unsigned Kind = 0) const override {
return &SystemZ::ADDR64BitRegClass;
}
diff --git a/llvm/lib/Target/VE/VERegisterInfo.cpp b/llvm/lib/Target/VE/VERegisterInfo.cpp
index f381b7d321598..99e1f61c088eb 100644
--- a/llvm/lib/Target/VE/VERegisterInfo.cpp
+++ b/llvm/lib/Target/VE/VERegisterInfo.cpp
@@ -93,8 +93,7 @@ BitVector VERegisterInfo::getReservedRegs(const MachineFunction &MF) const {
}
const TargetRegisterClass *
-VERegisterInfo::getPointerRegClass(const MachineFunction &MF,
- unsigned Kind) const {
+VERegisterInfo::getPointerRegClass(unsigned Kind) const {
return &VE::I64RegClass;
}
diff --git a/llvm/lib/Target/VE/VERegisterInfo.h b/llvm/lib/Target/VE/VERegisterInfo.h
index 3f6feedf42534..999dc856c9bd5 100644
--- a/llvm/lib/Target/VE/VERegisterInfo.h
+++ b/llvm/lib/Target/VE/VERegisterInfo.h
@@ -31,8 +31,7 @@ struct VERegisterInfo : public VEGenRegisterInfo {
BitVector getReservedRegs(const MachineFunction &MF) const override;
- const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
- unsigned Kind) const override;
+ const TargetRegisterClass *getPointerRegClass(unsigned Kind) const override;
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
unsigned FIOperandNum,
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
index 2f36e26066d81..27f7e1ada1250 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
@@ -278,7 +278,7 @@ void WebAssemblyFrameLowering::emitPrologue(MachineFunction &MF,
DebugLoc DL;
const TargetRegisterClass *PtrRC =
- MRI.getTargetRegisterInfo()->getPointerRegClass(MF);
+ MRI.getTargetRegisterInfo()->getPointerRegClass();
unsigned SPReg = getSPReg(MF);
if (StackSize)
SPReg = MRI.createVirtualRegister(PtrRC);
@@ -349,7 +349,7 @@ void WebAssemblyFrameLowering::emitEpilogue(MachineFunction &MF,
SPReg = FI->getBasePointerVreg();
} else if (StackSize) {
const TargetRegisterClass *PtrRC =
- MRI.getTargetRegisterInfo()->getPointerRegClass(MF);
+ MRI.getTargetRegisterInfo()->getPointerRegClass();
Register OffsetReg = MRI.createVirtualRegister(PtrRC);
BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg)
.addImm(StackSize);
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
index 18886ba570681..ebb5f555df67a 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
@@ -117,7 +117,7 @@ bool WebAssemblyRegisterInfo::eliminateFrameIndex(
if (FrameOffset) {
// Create i32/64.add SP, offset and make it the operand.
const TargetRegisterClass *PtrRC =
- MRI.getTargetRegisterInfo()->getPointerRegClass(MF);
+ MRI.getTargetRegisterInfo()->getPointerRegClass();
Register OffsetOp = MRI.createVirtualRegister(PtrRC);
BuildMI(MBB, *II, II->getDebugLoc(),
TII->get(WebAssemblyFrameLowering::getOpcConst(MF)),
@@ -149,10 +149,8 @@ WebAssemblyRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
}
const TargetRegisterClass *
-WebAssemblyRegisterInfo::getPointerRegClass(const MachineFunction &MF,
- unsigned Kind) const {
+WebAssemblyRegisterInfo::getPointerRegClass(unsigned Kind) const {
assert(Kind == 0 && "Only one kind of pointer on WebAssembly");
- if (MF.getSubtarget<WebAssemblySubtarget>().hasAddr64())
- return &WebAssembly::I64RegClass;
- return &WebAssembly::I32RegClass;
+ return TT.getArch() == Triple::wasm64 ? &WebAssembly::I64RegClass
+ : &WebAssembly::I32RegClass;
}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h
index d875e4b93603b..3a73ff6b1b3b0 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h
@@ -42,8 +42,7 @@ class WebAssemblyRegisterInfo final : public WebAssemblyGenRegisterInfo {
Register getFrameRegister(const MachineFunction &MF) const override;
const TargetRegisterClass *
- getPointerRegClass(const MachineFunction &MF,
- unsigned Kind = 0) const override;
+ getPointerRegClass(unsigned Kind = 0) const override;
// This does not apply to wasm.
const uint32_t *getNoPreservedMask() const override { return nullptr; }
};
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 7963dc1b755c9..c47bb3e67e625 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -61,6 +61,7 @@ X86RegisterInfo::X86RegisterInfo(const Triple &TT)
// Cache some information.
Is64Bit = TT.isArch64Bit();
+ IsTarget64BitLP64 = Is64Bit && !TT.isX32();
IsWin64 = Is64Bit && TT.isOSWindows();
IsUEFI64 = Is64Bit && TT.isUEFI();
@@ -192,13 +193,11 @@ X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
}
const TargetRegisterClass *
-X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
- unsigned Kind) const {
- const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
+X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
switch (Kind) {
default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
case 0: // Normal GPRs.
- if (Subtarget.isTarget64BitLP64())
+ if (IsTarget64BitLP64)
return &X86::GR64RegClass;
// If the target is 64bit but we have been told to use 32bit addresses,
// we can still use 64-bit register as long as we know the high bits
@@ -206,16 +205,16 @@ X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
// Reflect that in the returned register class.
return Is64Bit ? &X86::LOW32_ADDR_ACCESSRegClass : &X86::GR32RegClass;
case 1: // Normal GPRs except the stack pointer (for encoding reasons).
- if (Subtarget.isTarget64BitLP64())
+ if (IsTarget64BitLP64)
return &X86::GR64_NOSPRegClass;
// NOSP does not contain RIP, so no special case here.
return &X86::GR32_NOSPRegClass;
case 2: // NOREX GPRs.
- if (Subtarget.isTarget64BitLP64())
+ if (IsTarget64BitLP64)
return &X86::GR64_NOREXRegClass;
return &X86::GR32_NOREXRegClass;
case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
- if (Subtarget.isTarget64BitLP64())
+ if (IsTarget64BitLP64)
return &X86::GR64_NOREX_NOSPRegClass;
// NOSP does not contain RIP, so no special case here.
return &X86::GR32_NOREX_NOSPRegClass;
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.h b/llvm/lib/Target/X86/X86RegisterInfo.h
index d022e5ab87945..e646591663aca 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.h
+++ b/llvm/lib/Target/X86/X86RegisterInfo.h
@@ -28,6 +28,9 @@ class X86RegisterInfo final : public X86GenRegisterInfo {
///
bool Is64Bit;
+ /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
+ bool IsTarget64BitLP64;
+
/// IsWin64 - Is the target on of win64 flavours
///
bool IsWin64;
@@ -78,8 +81,7 @@ class X86RegisterInfo final : public X86GenRegisterInfo {
/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
/// values.
const TargetRegisterClass *
- getPointerRegClass(const MachineFunction &MF,
- unsigned Kind = 0) const override;
+ getPointerRegClass(unsigned Kind = 0) const override;
/// getCrossCopyRegClass - Returns a legal register class to copy a register
/// in the specified class to or from. Returns NULL if it is possible to copy
>From 09bb9e52212c8b837d00f04370bf2000ce7b0ea1 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 12 Sep 2025 17:47:20 +0900
Subject: [PATCH 2/2] Add explicit to constructors
Co-authored-by: Sergei Barannikov <barannikov88 at gmail.com>
---
llvm/lib/Target/ARM/ThumbRegisterInfo.h | 2 +-
llvm/lib/Target/Mips/Mips16RegisterInfo.h | 2 +-
llvm/lib/Target/Mips/MipsRegisterInfo.h | 2 +-
llvm/lib/Target/Mips/MipsSERegisterInfo.h | 2 +-
llvm/lib/Target/Sparc/SparcRegisterInfo.h | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/ARM/ThumbRegisterInfo.h b/llvm/lib/Target/ARM/ThumbRegisterInfo.h
index b077d302297ca..1512a09cae200 100644
--- a/llvm/lib/Target/ARM/ThumbRegisterInfo.h
+++ b/llvm/lib/Target/ARM/ThumbRegisterInfo.h
@@ -27,7 +27,7 @@ struct ThumbRegisterInfo : public ARMBaseRegisterInfo {
const bool IsThumb1Only;
public:
- ThumbRegisterInfo(const ARMSubtarget &STI);
+ explicit ThumbRegisterInfo(const ARMSubtarget &STI);
const TargetRegisterClass *
getLargestLegalSuperClass(const TargetRegisterClass *RC,
diff --git a/llvm/lib/Target/Mips/Mips16RegisterInfo.h b/llvm/lib/Target/Mips/Mips16RegisterInfo.h
index d0954ccba5912..29d08b4003ed4 100644
--- a/llvm/lib/Target/Mips/Mips16RegisterInfo.h
+++ b/llvm/lib/Target/Mips/Mips16RegisterInfo.h
@@ -18,7 +18,7 @@
namespace llvm {
class Mips16RegisterInfo : public MipsRegisterInfo {
public:
- Mips16RegisterInfo(const MipsSubtarget &STI);
+ explicit Mips16RegisterInfo(const MipsSubtarget &STI);
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.h b/llvm/lib/Target/Mips/MipsRegisterInfo.h
index 296ea82f99d7d..dbdb0501998bf 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.h
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.h
@@ -41,7 +41,7 @@ class MipsRegisterInfo : public MipsGenRegisterInfo {
GlobalPointer = 3,
};
- MipsRegisterInfo(const MipsSubtarget &STI);
+ explicit MipsRegisterInfo(const MipsSubtarget &STI);
/// Get PIC indirect call register
static unsigned getPICCallReg();
diff --git a/llvm/lib/Target/Mips/MipsSERegisterInfo.h b/llvm/lib/Target/Mips/MipsSERegisterInfo.h
index 5de20c4a8f111..93de2c778063a 100644
--- a/llvm/lib/Target/Mips/MipsSERegisterInfo.h
+++ b/llvm/lib/Target/Mips/MipsSERegisterInfo.h
@@ -20,7 +20,7 @@ namespace llvm {
class MipsSERegisterInfo : public MipsRegisterInfo {
public:
- MipsSERegisterInfo(const MipsSubtarget &STI);
+ explicit MipsSERegisterInfo(const MipsSubtarget &STI);
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.h b/llvm/lib/Target/Sparc/SparcRegisterInfo.h
index 0e9966d6f44b0..abd8baeff56a2 100644
--- a/llvm/lib/Target/Sparc/SparcRegisterInfo.h
+++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.h
@@ -26,7 +26,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
const bool Is64Bit;
public:
- SparcRegisterInfo(const SparcSubtarget &STI);
+ explicit SparcRegisterInfo(const SparcSubtarget &STI);
/// Code Generation virtual methods...
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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