[llvm] [TableGen] Add mapping from processor ID to resource index for packetizer (PR #158182)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 11 20:49:32 PDT 2025
https://github.com/LuoYuanke created https://github.com/llvm/llvm-project/pull/158182
Tablegen would generate code to access TargetResourceIndices with processor ID.
The TargetProcResourceIndexStart[] array is generated for each processor which
has itineraries. The processor which doesn't has itineraries is excluded from
the array. When a target has mixed processors, the processor ID may exceed the
array size and cause the error.
This patch is to generate a table mapping processor with itineraries to resource
index, so that scheduler can get the correct resource index with processor ID.
>From 5aa048c1adfa9d12a384e2cdf2754e919814ecc3 Mon Sep 17 00:00:00 2001
From: Yuanke Luo <ykluo at birentech.com>
Date: Thu, 11 Sep 2025 19:57:20 +0800
Subject: [PATCH] [TableGen] Add mapping from processor ID to resource index
for packetizer
Tablegen would generate code to access TargetResourceIndices with processor ID.
The TargetProcResourceIndexStart[] array is generated for each processor which
has itineraries. The processor which doesn't has itineraries is excluded from
the array. When a target has mixed processors, the processor ID may exceed the
array size and cause the error.
This patch is to generate a table mapping processor with itineraries to resource
index, so that scheduler can get the correct resource index with processor ID.
---
llvm/test/TableGen/DFAPacketizer.td | 31 ++++++++++++++++++++
llvm/utils/TableGen/DFAPacketizerEmitter.cpp | 19 +++++++++---
2 files changed, 46 insertions(+), 4 deletions(-)
create mode 100644 llvm/test/TableGen/DFAPacketizer.td
diff --git a/llvm/test/TableGen/DFAPacketizer.td b/llvm/test/TableGen/DFAPacketizer.td
new file mode 100644
index 0000000000000..b4c05c63811b5
--- /dev/null
+++ b/llvm/test/TableGen/DFAPacketizer.td
@@ -0,0 +1,31 @@
+// RUN: llvm-tblgen -gen-dfa-packetizer -I %p/../../include %s | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+def TestTarget : Target;
+
+def TestSchedModel : SchedMachineModel {
+ let CompleteModel = 0;
+}
+
+def TestProcessor1 : ProcessorModel<"testprocessor1", TestSchedModel, []>;
+
+def FU0 : FuncUnit;
+def FU1 : FuncUnit;
+
+def OP0 : InstrItinClass;
+def OP1 : InstrItinClass;
+
+def Itin {
+ list<InstrItinData> ItinList = [
+ InstrItinData<OP0, [InstrStage<1, [FU0]>]>,
+ InstrItinData<OP1, [InstrStage<1, [FU1]>]>,
+ ];
+}
+
+// CHECK: std::map<unsigned, unsigned> TestTargetProcIdToResourceIndexStartMapping = {
+// CHECK-NEXT: { 2, 1 }, // TestItinerariesModel
+// CHECK-NEXT: };
+
+def TestItineraries: ProcessorItineraries<[], [], Itin.ItinList>;
+def TestProcessor2 : Processor<"testprocessor2", TestItineraries, []>;
diff --git a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
index 8cb2c22736f8a..0fd30411451a2 100644
--- a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
+++ b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
@@ -256,6 +256,16 @@ void DFAPacketizerEmitter::emitForItineraries(
}
OS << "\n};\n\n";
+ // Output the mapping from proc ID to ResourceIndexStart
+ Idx = 1;
+ OS << "std::map<unsigned, unsigned> " << TargetName << DFAName
+ << "ProcIdToResourceIndexStartMapping = {\n";
+ for (const CodeGenProcModel *Model : ProcModels) {
+ OS << " { " << Model->Index << ", " << Idx++ << " }, // "
+ << Model->ModelName << "\n";
+ }
+ OS << "};\n\n";
+
// And the mapping from Itinerary index into the previous table.
OS << "constexpr unsigned " << TargetName << DFAName
<< "ProcResourceIndexStart[] = {\n";
@@ -339,16 +349,17 @@ void DFAPacketizerEmitter::emitForItineraries(
std::string SubTargetClassName = TargetName + "GenSubtargetInfo";
OS << "namespace llvm {\n";
- OS << "DFAPacketizer *" << SubTargetClassName << "::"
- << "create" << DFAName
+ OS << "DFAPacketizer *" << SubTargetClassName << "::" << "create" << DFAName
<< "DFAPacketizer(const InstrItineraryData *IID) const {\n"
<< " static Automaton<uint64_t> A(ArrayRef<" << TargetAndDFAName
<< "Transition>(" << TargetAndDFAName << "Transitions), "
<< TargetAndDFAName << "TransitionInfo);\n"
+ << " unsigned Index = " << TargetName << DFAName
+ << "ProcIdToResourceIndexStartMapping[IID->SchedModel.ProcID];\n"
<< " unsigned ProcResIdxStart = " << TargetAndDFAName
- << "ProcResourceIndexStart[IID->SchedModel.ProcID];\n"
+ << "ProcResourceIndexStart[Index];\n"
<< " unsigned ProcResIdxNum = " << TargetAndDFAName
- << "ProcResourceIndexStart[IID->SchedModel.ProcID + 1] - "
+ << "ProcResourceIndexStart[Index + 1] - "
"ProcResIdxStart;\n"
<< " return new DFAPacketizer(IID, A, {&" << TargetAndDFAName
<< "ResourceIndices[ProcResIdxStart], ProcResIdxNum});\n"
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