[llvm] [NFC][PowerPC] Pre-commit testcases for locking down the xxsel instructions for ternary(A, X, eqv(B, C)), ternary(A, X, not(C)), ternary(A, X, not(B)), ternary(A, X, nand(B, C)) and ternary(A, X, nor(B, C)) patterns (PR #158091)
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Thu Sep 11 10:10:49 PDT 2025
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llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-powerpc
Author: Tony Varghese (tonykuttai)
<details>
<summary>Changes</summary>
Pre-commit test case for exploitation of `xxsel` for ternary operations of the pattern. This adds support for v4i32, v2i64, v16i8 and v8i16 operand types for the following patterns.
The following are the patterns involved in the change:
```
ternary(A, and(B,C), nor(B,C))
ternary(A, B, nor(B,C))
ternary(A, C, nor(B,C))
ternary(A, xor(B,C), nor(B,C))
ternary(A, not(C), nor(B,C))
ternary(A, not(B), nor(B,C))
ternary(A, nand(B,C), nor(B,C))
ternary(A, or(B,C), eqv(B,C))
ternary(A, nor(B,C), eqv(B,C))
ternary(A, not(C), eqv(B,C))
ternary(A, nand(B,C), eqv(B,C))
ternary(A, and(B,C), not(C))
ternary(A, B, not(C))
ternary(A, xor(B,C), not(C))
ternary(A, or(B,C), not(C))
ternary(A, not(B), not(C))
ternary(A, nand(B,C), not(C))
ternary(A, and(B,C), not(B))
ternary(A, xor(B,C), not(B))
ternary(A, or(B,C), not(B))
ternary(A, nand(B,C), not(B))
ternary(A, B, nand(B,C))
ternary(A, C, nand(B,C))
ternary(A, xor(B,C), nand(B,C))
ternary(A, or(B,C), nand(B,C))
ternary(A, eqv(B,C), nand(B,C))
```
Exploitation of `xxeval` for the above patterns to be added as a follow up.
---
Patch is 82.26 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/158091.diff
5 Files Affected:
- (added) llvm/test/CodeGen/PowerPC/xxeval-vselect-x-eqv.ll (+327)
- (added) llvm/test/CodeGen/PowerPC/xxeval-vselect-x-nand.ll (+384)
- (added) llvm/test/CodeGen/PowerPC/xxeval-vselect-x-nor.ll (+538)
- (added) llvm/test/CodeGen/PowerPC/xxeval-vselect-x-not-b.ll (+307)
- (added) llvm/test/CodeGen/PowerPC/xxeval-vselect-x-not-c.ll (+445)
``````````diff
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-eqv.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-eqv.ll
new file mode 100644
index 0000000000000..7fa576f599dc4
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-eqv.ll
@@ -0,0 +1,327 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; Test file to verify the emission of Vector Evaluate instructions when ternary operators are used.
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; Function to test ternary(A, or(B, C), eqv(B, C)) for <4 x i32>
+define <4 x i32> @ternary_A_or_BC_eqv_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
+; CHECK-LABEL: ternary_A_or_BC_eqv_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxleqv v5, v5, v5
+; CHECK-NEXT: xxlor vs0, v3, v4
+; CHECK-NEXT: xxleqv vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+entry:
+ %or = or <4 x i32> %B, %C
+ %xor = xor <4 x i32> %B, %C
+ %eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
+ %res = select <4 x i1> %A, <4 x i32> %or, <4 x i32> %eqv
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, or(B, C), eqv(B, C)) for <2 x i64>
+define <2 x i64> @ternary_A_or_BC_eqv_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
+; CHECK-LABEL: ternary_A_or_BC_eqv_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlor vs0, v3, v4
+; CHECK-NEXT: xxleqv vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+entry:
+ %or = or <2 x i64> %B, %C
+ %xor = xor <2 x i64> %B, %C
+ %eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
+ %res = select <2 x i1> %A, <2 x i64> %or, <2 x i64> %eqv
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, or(B, C), eqv(B, C)) for <16 x i8>
+define <16 x i8> @ternary_A_or_BC_eqv_BC_16x8(<16 x i1> %A, <16 x i8> %B, <16 x i8> %C) {
+; CHECK-LABEL: ternary_A_or_BC_eqv_BC_16x8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltib v5, 7
+; CHECK-NEXT: xxlor vs0, v3, v4
+; CHECK-NEXT: xxleqv vs1, v3, v4
+; CHECK-NEXT: vslb v2, v2, v5
+; CHECK-NEXT: vsrab v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+entry:
+ %or = or <16 x i8> %B, %C
+ %xor = xor <16 x i8> %B, %C
+ %eqv = xor <16 x i8> %xor, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> ; Vector eqv operation
+ %res = select <16 x i1> %A, <16 x i8> %or, <16 x i8> %eqv
+ ret <16 x i8> %res
+}
+
+; Function to test ternary(A, or(B, C), eqv(B, C)) for <8 x i16>
+define <8 x i16> @ternary_A_or_BC_eqv_BC_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i16> %C) {
+; CHECK-LABEL: ternary_A_or_BC_eqv_BC_8x16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 983055
+; CHECK-NEXT: xxlor vs0, v3, v4
+; CHECK-NEXT: xxleqv vs1, v3, v4
+; CHECK-NEXT: vslh v2, v2, v5
+; CHECK-NEXT: vsrah v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+entry:
+ %or = or <8 x i16> %B, %C
+ %xor = xor <8 x i16> %B, %C
+ %eqv = xor <8 x i16> %xor, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> ; Vector eqv operation
+ %res = select <8 x i1> %A, <8 x i16> %or, <8 x i16> %eqv
+ ret <8 x i16> %res
+}
+
+; Function to test ternary(A, nor(B, C), eqv(B, C)) for <4 x i32>
+define <4 x i32> @ternary_A_nor_BC_eqv_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
+; CHECK-LABEL: ternary_A_nor_BC_eqv_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxleqv v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxleqv vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+entry:
+ %or = or <4 x i32> %B, %C
+ %nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector NOR operation
+ %xor = xor <4 x i32> %B, %C
+ %eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
+ %res = select <4 x i1> %A, <4 x i32> %nor, <4 x i32> %eqv
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, nor(B, C), eqv(B, C)) for <2 x i64>
+define <2 x i64> @ternary_A_nor_BC_eqv_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
+; CHECK-LABEL: ternary_A_nor_BC_eqv_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxleqv vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+entry:
+ %or = or <2 x i64> %B, %C
+ %nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; Vector NOR operation
+ %xor = xor <2 x i64> %B, %C
+ %eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
+ %res = select <2 x i1> %A, <2 x i64> %nor, <2 x i64> %eqv
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, nor(B, C), eqv(B, C)) for <16 x i8>
+define <16 x i8> @ternary_A_nor_BC_eqv_BC_16x8(<16 x i1> %A, <16 x i8> %B, <16 x i8> %C) {
+; CHECK-LABEL: ternary_A_nor_BC_eqv_BC_16x8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltib v5, 7
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxleqv vs1, v3, v4
+; CHECK-NEXT: vslb v2, v2, v5
+; CHECK-NEXT: vsrab v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+entry:
+ %or = or <16 x i8> %B, %C
+ %nor = xor <16 x i8> %or, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> ; Vector NOR operation
+ %xor = xor <16 x i8> %B, %C
+ %eqv = xor <16 x i8> %xor, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> ; Vector eqv operation
+ %res = select <16 x i1> %A, <16 x i8> %nor, <16 x i8> %eqv
+ ret <16 x i8> %res
+}
+
+; Function to test ternary(A, nor(B, C), eqv(B, C)) for <8 x i16>
+define <8 x i16> @ternary_A_nor_BC_eqv_BC_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i16> %C) {
+; CHECK-LABEL: ternary_A_nor_BC_eqv_BC_8x16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 983055
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxleqv vs1, v3, v4
+; CHECK-NEXT: vslh v2, v2, v5
+; CHECK-NEXT: vsrah v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+entry:
+ %or = or <8 x i16> %B, %C
+ %nor = xor <8 x i16> %or, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> ; Vector NOR operation
+ %xor = xor <8 x i16> %B, %C
+ %eqv = xor <8 x i16> %xor, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> ; Vector eqv operation
+ %res = select <8 x i1> %A, <8 x i16> %nor, <8 x i16> %eqv
+ ret <8 x i16> %res
+}
+
+; Function to test ternary(A, not(C), eqv(B, C)) for <4 x i32>
+define <4 x i32> @ternary_A_not_C_eqv_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
+; CHECK-LABEL: ternary_A_not_C_eqv_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxleqv v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: xxleqv vs1, v4, v3
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+entry:
+ %not = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
+ %xor = xor <4 x i32> %B, %C
+ %eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
+ %res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %eqv
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, not(C), eqv(B, C)) for <2 x i64>
+define <2 x i64> @ternary_A_not_C_eqv_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
+; CHECK-LABEL: ternary_A_not_C_eqv_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: xxleqv vs1, v4, v3
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+entry:
+ %not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
+ %xor = xor <2 x i64> %B, %C
+ %eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
+ %res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %eqv
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, not(C), eqv(B, C)) for <16 x i8>
+define <16 x i8> @ternary_A_not_C_eqv_BC_16x8(<16 x i1> %A, <16 x i8> %B, <16 x i8> %C) {
+; CHECK-LABEL: ternary_A_not_C_eqv_BC_16x8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltib v5, 7
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: xxleqv vs1, v4, v3
+; CHECK-NEXT: vslb v2, v2, v5
+; CHECK-NEXT: vsrab v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+entry:
+ %not = xor <16 x i8> %C, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> ; Vector not operation
+ %xor = xor <16 x i8> %B, %C
+ %eqv = xor <16 x i8> %xor, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> ; Vector eqv operation
+ %res = select <16 x i1> %A, <16 x i8> %not, <16 x i8> %eqv
+ ret <16 x i8> %res
+}
+
+; Function to test ternary(A, not(C), eqv(B, C)) for <8 x i16>
+define <8 x i16> @ternary_A_not_C_eqv_BC_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i16> %C) {
+; CHECK-LABEL: ternary_A_not_C_eqv_BC_8x16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 983055
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: xxleqv vs1, v4, v3
+; CHECK-NEXT: vslh v2, v2, v5
+; CHECK-NEXT: vsrah v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+entry:
+ %not = xor <8 x i16> %C, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> ; Vector not operation
+ %xor = xor <8 x i16> %B, %C
+ %eqv = xor <8 x i16> %xor, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> ; Vector eqv operation
+ %res = select <8 x i1> %A, <8 x i16> %not, <8 x i16> %eqv
+ ret <8 x i16> %res
+}
+
+; Function to test ternary(A, nand(B, C), eqv(B, C)) for <4 x i32>
+define <4 x i32> @ternary_A_nand_BC_eqv_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
+; CHECK-LABEL: ternary_A_nand_BC_eqv_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxleqv v5, v5, v5
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: xxleqv vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+entry:
+ %and = and <4 x i32> %B, %C
+ %nand = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector nand operation
+ %xor = xor <4 x i32> %B, %C
+ %eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
+ %res = select <4 x i1> %A, <4 x i32> %nand, <4 x i32> %eqv
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, nand(B, C), eqv(B, C)) for <2 x i64>
+define <2 x i64> @ternary_A_nand_BC_eqv_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
+; CHECK-LABEL: ternary_A_nand_BC_eqv_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: xxleqv vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+entry:
+ %and = and <2 x i64> %B, %C
+ %nand = xor <2 x i64> %and, <i64 -1, i64 -1> ; Vector nand operation
+ %xor = xor <2 x i64> %B, %C
+ %eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
+ %res = select <2 x i1> %A, <2 x i64> %nand, <2 x i64> %eqv
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, nand(B, C), eqv(B, C)) for <16 x i8>
+define <16 x i8> @ternary_A_nand_BC_eqv_BC_16x8(<16 x i1> %A, <16 x i8> %B, <16 x i8> %C) {
+; CHECK-LABEL: ternary_A_nand_BC_eqv_BC_16x8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltib v5, 7
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: xxleqv vs1, v3, v4
+; CHECK-NEXT: vslb v2, v2, v5
+; CHECK-NEXT: vsrab v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+entry:
+ %and = and <16 x i8> %B, %C
+ %nand = xor <16 x i8> %and, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> ; Vector nand operation
+ %xor = xor <16 x i8> %B, %C
+ %eqv = xor <16 x i8> %xor, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> ; Vector eqv operation
+ %res = select <16 x i1> %A, <16 x i8> %nand, <16 x i8> %eqv
+ ret <16 x i8> %res
+}
+
+; Function to test ternary(A, nand(B, C), eqv(B, C)) for <8 x i16>
+define <8 x i16> @ternary_A_nand_BC_eqv_BC_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i16> %C) {
+; CHECK-LABEL: ternary_A_nand_BC_eqv_BC_8x16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 983055
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: xxleqv vs1, v3, v4
+; CHECK-NEXT: vslh v2, v2, v5
+; CHECK-NEXT: vsrah v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+entry:
+ %and = and <8 x i16> %B, %C
+ %nand = xor <8 x i16> %and, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> ; Vector nand operation
+ %xor = xor <8 x i16> %B, %C
+ %eqv = xor <8 x i16> %xor, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> ; Vector eqv operation
+ %res = select <8 x i1> %A, <8 x i16> %nand, <8 x i16> %eqv
+ ret <8 x i16> %res
+}
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-nand.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-nand.ll
new file mode 100644
index 0000000000000..7a6733d3b5510
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-nand.ll
@@ -0,0 +1,384 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; Test file to verify the emission of Vector Evaluate instructions when ternary operators are used.
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; Function to test ternary(A, B, nand(B, C)) for <4 x i32>
+define <4 x i32> @ternary_A_B_nand_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
+; CHECK-LABEL: ternary_A_B_nand_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxleqv v5, v5, v5
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK-NEXT: blr
+entry:
+ %and = and <4 x i32> %B, %C
+ %nand = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector nand operation
+ %res = select <4 x i1> %A, <4 x i32> %B, <4 x i32> %nand
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, B, nand(B, C)) for <2 x i64>
+define <2 x i64> @ternary_A_B_nand_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
+; CHECK-LABEL: ternary_A_B_nand_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK-NEXT: blr
+entry:
+ %and = and <2 x i64> %B, %C
+ %nand = xor <2 x i64> %and, <i64 -1, i64 -1> ; Vector nand operation
+ %res = select <2 x i1> %A, <2 x i64> %B, <2 x i64> %nand
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, B, nand(B, C)) for <16 x i8>
+define <16 x i8> @ternary_A_B_nand_BC_16x8(<16 x i1> %A, <16 x i8> %B, <16 x i8> %C) {
+; CHECK-LABEL: ternary_A_B_nand_BC_16x8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltib v5, 7
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: vslb v2, v2, v5
+; CHECK-NEXT: vsrab v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK-NEXT: blr
+entry:
+ %and = and <16 x i8> %B, %C
+ %nand = xor <16 x i8> %and, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> ; Vector nand operation
+ %res = select <16 x i1> %A, <16 x i8> %B, <16 x i8> %nand
+ ret <16 x i8> %res
+}
+
+; Function to test ternary(A, B, nand(B, C)) for <8 x i16>
+define <8 x i16> @ternary_A_B_nand_BC_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i16> %C) {
+; CHECK-LABEL: ternary_A_B_nand_BC_8x16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 983055
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: vslh v2, v2, v5
+; CHECK-NEXT: vsrah v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK-NEXT: blr
+entry:
+ %and = and <8 x i16> %B, %C
+ %nand = xor <8 x i16> %and, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> ; Vector nand operation
+ %res = select <8 x i1> %A, <8 x i16> %B, <8 x i16> %nand
+ ret <8 x i16> %res
+}
+
+; Function to test ternary(A, C, nand(B, C)) for <4 x i32>
+define <4 x i32> @ternary_A_C_nand_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
+; CHECK-LABEL: ternary_A_C_nand_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxleqv v5, v5, v5
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK-NEXT: blr
+entry:
+ %and = and <4 x i32> %B, %C
+ %nand = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector nand operation
+ %res = select <4 x i1> %A, <4 x i32> %C, <4 x i32> %nand
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, C, nand(B, C)) for <2 x i64>
+define <2 x i64> @ternary_A_C_nand_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
+; CHECK-LABEL: ternary_A_C_nand_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK-NEXT: blr
+entry:
+ %and = and <2 x i64> %B, %C
+ %nand = xor <2 x i64> %and, <i64 -1, i64 -1> ; Vector nand operation
+ %res = select <2 x i1> %A, <2 x i64> %C, <2 x i64> %nand
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, C, nand(B, C)) for <16 x i8>
+define <16 x i8> @ternary_A_C_nand_BC_16x8(<16 x i1> %A, <16 x i8> %B, <16 x i8> %C) {
+; CHECK-LABEL: ternary_A_C_nand_BC_16x8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltib v5, 7
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: vslb v2, v2, v5
+; CHECK-NEXT: vsrab v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK-NEXT: blr
+entry:
+ %and = and <16 x i8> %B, %C
+ %nand = xor <16 x i8> %and, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> ; Vector nand operation
+ %res = select <16 x i1> %A, <16 x i8> %C, <16 x i8> %nand
+ ret <16 x i8> %res
+}
+
+; Function to test ternary(A, C, nand(B, C)) for <8 x i16>
+define <8 x i16> @ternary_A_C_nand_BC_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i16> %C) {
+; CHECK-LABEL: ternary_A_C_nand_BC_8x16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 983055
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: vslh v2, v2, v5
+; CHECK-NEXT: vsrah v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK-NEXT: blr
+entry:
+ %and = and <8 x i16> %B, %C
+ %nand = xor <8 x i16> %and, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/158091
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