[llvm] [X86] Don't rely on global -fp-contract=fast on X86 CodeGen tests (PR #158026)
Mikołaj Piróg via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 11 03:19:55 PDT 2025
https://github.com/mikolaj-pirog created https://github.com/llvm/llvm-project/pull/158026
IR has the `contract` to indicate that contraction is allowed. Testing shouldn't rely on global flag to perform contraction. This is a prerequisite before making backends rely only on the IR to perform contraction. See more here: https://discourse.llvm.org/t/allowfpopfusion-vs-sdnodeflags-hasallowcontract/80909/5
>From 53d8ce509bd363bebeb76d85306b434ff84f378d Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Thu, 11 Sep 2025 11:58:34 +0200
Subject: [PATCH] Don't rely on global contract flag on tests
---
llvm/test/CodeGen/X86/avx512-fma.ll | 62 +--
.../X86/avx512fp16-combine-vfmac-fadd.ll | 52 +--
.../X86/avx512fp16-combine-vfmulc-fadd.ll | 2 +-
.../X86/avx512fp16-combine-xor-vfmulc-fadd.ll | 2 +-
.../X86/avx512fp16-combine-xor-vfmulc.ll | 10 +-
.../CodeGen/X86/dag-combiner-fma-folding.ll | 2 +-
llvm/test/CodeGen/X86/fma-do-not-commute.ll | 6 +-
llvm/test/CodeGen/X86/fma_patterns.ll | 390 +++++++++---------
llvm/test/CodeGen/X86/fma_patterns_wide.ll | 164 ++++----
.../X86/fold-int-pow2-with-fmul-or-fdiv.ll | 14 +-
llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll | 50 +--
11 files changed, 373 insertions(+), 381 deletions(-)
diff --git a/llvm/test/CodeGen/X86/avx512-fma.ll b/llvm/test/CodeGen/X86/avx512-fma.ll
index 97f8e5f4ea16c..54343ee771ff7 100644
--- a/llvm/test/CodeGen/X86/avx512-fma.ll
+++ b/llvm/test/CodeGen/X86/avx512-fma.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f -fp-contract=fast | FileCheck %s --check-prefix=ALL --check-prefix=KNL
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx -fp-contract=fast | FileCheck %s --check-prefix=ALL --check-prefix=SKX
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=KNL
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s --check-prefix=ALL --check-prefix=SKX
define <16 x float> @test_x86_fmadd_ps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
; ALL-LABEL: test_x86_fmadd_ps_z:
; ALL: ## %bb.0:
; ALL-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; ALL-NEXT: retq
- %x = fmul <16 x float> %a0, %a1
- %res = fadd <16 x float> %x, %a2
+ %x = fmul contract <16 x float> %a0, %a1
+ %res = fadd contract <16 x float> %x, %a2
ret <16 x float> %res
}
@@ -17,8 +17,8 @@ define <16 x float> @test_x86_fmsub_ps_z(<16 x float> %a0, <16 x float> %a1, <16
; ALL: ## %bb.0:
; ALL-NEXT: vfmsub213ps {{.*#+}} zmm0 = (zmm1 * zmm0) - zmm2
; ALL-NEXT: retq
- %x = fmul <16 x float> %a0, %a1
- %res = fsub <16 x float> %x, %a2
+ %x = fmul contract <16 x float> %a0, %a1
+ %res = fsub contract <16 x float> %x, %a2
ret <16 x float> %res
}
@@ -27,8 +27,8 @@ define <16 x float> @test_x86_fnmadd_ps_z(<16 x float> %a0, <16 x float> %a1, <1
; ALL: ## %bb.0:
; ALL-NEXT: vfnmadd213ps {{.*#+}} zmm0 = -(zmm1 * zmm0) + zmm2
; ALL-NEXT: retq
- %x = fmul <16 x float> %a0, %a1
- %res = fsub <16 x float> %a2, %x
+ %x = fmul contract <16 x float> %a0, %a1
+ %res = fsub contract <16 x float> %a2, %x
ret <16 x float> %res
}
@@ -37,12 +37,12 @@ define <16 x float> @test_x86_fnmsub_ps_z(<16 x float> %a0, <16 x float> %a1, <1
; ALL: ## %bb.0:
; ALL-NEXT: vfnmsub213ps {{.*#+}} zmm0 = -(zmm1 * zmm0) - zmm2
; ALL-NEXT: retq
- %x = fmul <16 x float> %a0, %a1
- %y = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00,
+ %x = fmul contract <16 x float> %a0, %a1
+ %y = fsub contract <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00,
float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00,
float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00,
float -0.000000e+00>, %x
- %res = fsub <16 x float> %y, %a2
+ %res = fsub contract <16 x float> %y, %a2
ret <16 x float> %res
}
@@ -51,8 +51,8 @@ define <8 x double> @test_x86_fmadd_pd_z(<8 x double> %a0, <8 x double> %a1, <8
; ALL: ## %bb.0:
; ALL-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; ALL-NEXT: retq
- %x = fmul <8 x double> %a0, %a1
- %res = fadd <8 x double> %x, %a2
+ %x = fmul contract <8 x double> %a0, %a1
+ %res = fadd contract <8 x double> %x, %a2
ret <8 x double> %res
}
@@ -61,8 +61,8 @@ define <8 x double> @test_x86_fmsub_pd_z(<8 x double> %a0, <8 x double> %a1, <8
; ALL: ## %bb.0:
; ALL-NEXT: vfmsub213pd {{.*#+}} zmm0 = (zmm1 * zmm0) - zmm2
; ALL-NEXT: retq
- %x = fmul <8 x double> %a0, %a1
- %res = fsub <8 x double> %x, %a2
+ %x = fmul contract <8 x double> %a0, %a1
+ %res = fsub contract <8 x double> %x, %a2
ret <8 x double> %res
}
@@ -71,8 +71,8 @@ define double @test_x86_fmsub_213(double %a0, double %a1, double %a2) {
; ALL: ## %bb.0:
; ALL-NEXT: vfmsub213sd {{.*#+}} xmm0 = (xmm1 * xmm0) - xmm2
; ALL-NEXT: retq
- %x = fmul double %a0, %a1
- %res = fsub double %x, %a2
+ %x = fmul contract double %a0, %a1
+ %res = fsub contract double %x, %a2
ret double %res
}
@@ -82,8 +82,8 @@ define double @test_x86_fmsub_213_m(double %a0, double %a1, ptr %a2_ptr) {
; ALL-NEXT: vfmsub213sd {{.*#+}} xmm0 = (xmm1 * xmm0) - mem
; ALL-NEXT: retq
%a2 = load double , ptr%a2_ptr
- %x = fmul double %a0, %a1
- %res = fsub double %x, %a2
+ %x = fmul contract double %a0, %a1
+ %res = fsub contract double %x, %a2
ret double %res
}
@@ -93,8 +93,8 @@ define double @test_x86_fmsub_231_m(double %a0, double %a1, ptr %a2_ptr) {
; ALL-NEXT: vfmsub132sd {{.*#+}} xmm0 = (xmm0 * mem) - xmm1
; ALL-NEXT: retq
%a2 = load double , ptr%a2_ptr
- %x = fmul double %a0, %a2
- %res = fsub double %x, %a1
+ %x = fmul contract double %a0, %a2
+ %res = fsub contract double %x, %a1
ret double %res
}
@@ -103,8 +103,8 @@ define <16 x float> @test231_br(<16 x float> %a1, <16 x float> %a2) nounwind {
; ALL: ## %bb.0:
; ALL-NEXT: vfmadd132ps {{.*#+}} zmm0 = (zmm0 * mem) + zmm1
; ALL-NEXT: retq
- %b1 = fmul <16 x float> %a1, <float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000>
- %b2 = fadd <16 x float> %b1, %a2
+ %b1 = fmul contract <16 x float> %a1, <float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000>
+ %b2 = fadd contract <16 x float> %b1, %a2
ret <16 x float> %b2
}
@@ -113,8 +113,8 @@ define <16 x float> @test213_br(<16 x float> %a1, <16 x float> %a2) nounwind {
; ALL: ## %bb.0:
; ALL-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + mem
; ALL-NEXT: retq
- %b1 = fmul <16 x float> %a1, %a2
- %b2 = fadd <16 x float> %b1, <float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000>
+ %b1 = fmul contract <16 x float> %a1, %a2
+ %b2 = fadd contract <16 x float> %b1, <float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000>
ret <16 x float> %b2
}
@@ -135,8 +135,8 @@ define <16 x float> @test_x86_fmadd132_ps(<16 x float> %a0, <16 x float> %a1, pt
; SKX-NEXT: vfmadd132ps {{.*#+}} zmm0 {%k1} = (zmm0 * mem) + zmm1
; SKX-NEXT: retq
%a2 = load <16 x float>,ptr%a2_ptrt,align 1
- %x = fmul <16 x float> %a0, %a2
- %y = fadd <16 x float> %x, %a1
+ %x = fmul contract <16 x float> %a0, %a2
+ %y = fadd contract <16 x float> %x, %a1
%res = select <16 x i1> %mask, <16 x float> %y, <16 x float> %a0
ret <16 x float> %res
}
@@ -160,8 +160,8 @@ define <16 x float> @test_x86_fmadd231_ps(<16 x float> %a0, <16 x float> %a1, pt
; SKX-NEXT: vmovaps %zmm1, %zmm0
; SKX-NEXT: retq
%a2 = load <16 x float>,ptr%a2_ptrt,align 1
- %x = fmul <16 x float> %a0, %a2
- %y = fadd <16 x float> %x, %a1
+ %x = fmul contract <16 x float> %a0, %a2
+ %y = fadd contract <16 x float> %x, %a1
%res = select <16 x i1> %mask, <16 x float> %y, <16 x float> %a1
ret <16 x float> %res
}
@@ -185,8 +185,8 @@ define <16 x float> @test_x86_fmadd213_ps(<16 x float> %a0, <16 x float> %a1, pt
; SKX-NEXT: vmovaps %zmm1, %zmm0
; SKX-NEXT: retq
%a2 = load <16 x float>,ptr%a2_ptrt,align 1
- %x = fmul <16 x float> %a1, %a0
- %y = fadd <16 x float> %x, %a2
+ %x = fmul contract <16 x float> %a1, %a0
+ %y = fadd contract <16 x float> %x, %a2
%res = select <16 x i1> %mask, <16 x float> %y, <16 x float> %a1
ret <16 x float> %res
}
diff --git a/llvm/test/CodeGen/X86/avx512fp16-combine-vfmac-fadd.ll b/llvm/test/CodeGen/X86/avx512fp16-combine-vfmac-fadd.ll
index 36b95e744ba14..52e9507d43a1f 100644
--- a/llvm/test/CodeGen/X86/avx512fp16-combine-vfmac-fadd.ll
+++ b/llvm/test/CodeGen/X86/avx512fp16-combine-vfmac-fadd.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown --fp-contract=fast --enable-no-signed-zeros-fp-math -mattr=avx512fp16,avx512vl | FileCheck %s --check-prefixes=CHECK,NO-SZ
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown --fp-contract=fast -mattr=avx512fp16,avx512vl | FileCheck %s --check-prefixes=CHECK,HAS-SZ
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown --enable-no-signed-zeros-fp-math -mattr=avx512fp16,avx512vl | FileCheck %s --check-prefixes=CHECK,NO-SZ
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16,avx512vl | FileCheck %s --check-prefixes=CHECK,HAS-SZ
; FADD(acc, FMA(a, b, +0.0)) can be combined to FMA(a, b, acc) if the nsz flag set.
define dso_local <32 x half> @test1(<32 x half> %acc, <32 x half> %a, <32 x half> %b) {
@@ -18,9 +18,9 @@ define dso_local <32 x half> @test1(<32 x half> %acc, <32 x half> %a, <32 x half
entry:
%0 = bitcast <32 x half> %a to <16 x float>
%1 = bitcast <32 x half> %b to <16 x float>
- %2 = tail call <16 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
+ %2 = tail call contract <16 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
%3 = bitcast <16 x float> %2 to <32 x half>
- %add.i = fadd <32 x half> %3, %acc
+ %add.i = fadd contract <32 x half> %3, %acc
ret <32 x half> %add.i
}
@@ -39,9 +39,9 @@ define dso_local <32 x half> @test2(<32 x half> %acc, <32 x half> %a, <32 x half
entry:
%0 = bitcast <32 x half> %a to <16 x float>
%1 = bitcast <32 x half> %b to <16 x float>
- %2 = tail call <16 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
+ %2 = tail call contract <16 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
%3 = bitcast <16 x float> %2 to <32 x half>
- %add.i = fadd <32 x half> %3, %acc
+ %add.i = fadd contract <32 x half> %3, %acc
ret <32 x half> %add.i
}
@@ -60,9 +60,9 @@ define dso_local <16 x half> @test3(<16 x half> %acc, <16 x half> %a, <16 x half
entry:
%0 = bitcast <16 x half> %a to <8 x float>
%1 = bitcast <16 x half> %b to <8 x float>
- %2 = tail call <8 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> zeroinitializer, i8 -1)
+ %2 = tail call contract <8 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> zeroinitializer, i8 -1)
%3 = bitcast <8 x float> %2 to <16 x half>
- %add.i = fadd <16 x half> %3, %acc
+ %add.i = fadd contract <16 x half> %3, %acc
ret <16 x half> %add.i
}
@@ -81,9 +81,9 @@ define dso_local <16 x half> @test4(<16 x half> %acc, <16 x half> %a, <16 x half
entry:
%0 = bitcast <16 x half> %a to <8 x float>
%1 = bitcast <16 x half> %b to <8 x float>
- %2 = tail call <8 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> zeroinitializer, i8 -1)
+ %2 = tail call contract <8 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> zeroinitializer, i8 -1)
%3 = bitcast <8 x float> %2 to <16 x half>
- %add.i = fadd <16 x half> %3, %acc
+ %add.i = fadd contract <16 x half> %3, %acc
ret <16 x half> %add.i
}
@@ -102,9 +102,9 @@ define dso_local <8 x half> @test5(<8 x half> %acc, <8 x half> %a, <8 x half> %b
entry:
%0 = bitcast <8 x half> %a to <4 x float>
%1 = bitcast <8 x half> %b to <4 x float>
- %2 = tail call <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> zeroinitializer, i8 -1)
+ %2 = tail call contract <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> zeroinitializer, i8 -1)
%3 = bitcast <4 x float> %2 to <8 x half>
- %add.i = fadd <8 x half> %3, %acc
+ %add.i = fadd contract <8 x half> %3, %acc
ret <8 x half> %add.i
}
@@ -123,9 +123,9 @@ define dso_local <8 x half> @test6(<8 x half> %acc, <8 x half> %a, <8 x half> %b
entry:
%0 = bitcast <8 x half> %a to <4 x float>
%1 = bitcast <8 x half> %b to <4 x float>
- %2 = tail call <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> zeroinitializer, i8 -1)
+ %2 = tail call contract <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> zeroinitializer, i8 -1)
%3 = bitcast <4 x float> %2 to <8 x half>
- %add.i = fadd <8 x half> %3, %acc
+ %add.i = fadd contract <8 x half> %3, %acc
ret <8 x half> %add.i
}
@@ -138,9 +138,9 @@ define dso_local <32 x half> @test13(<32 x half> %acc, <32 x half> %a, <32 x hal
entry:
%0 = bitcast <32 x half> %a to <16 x float>
%1 = bitcast <32 x half> %b to <16 x float>
- %2 = tail call <16 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i16 -1, i32 4)
+ %2 = tail call contract <16 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i16 -1, i32 4)
%3 = bitcast <16 x float> %2 to <32 x half>
- %add.i = fadd <32 x half> %3, %acc
+ %add.i = fadd contract <32 x half> %3, %acc
ret <32 x half> %add.i
}
@@ -152,9 +152,9 @@ define dso_local <32 x half> @test14(<32 x half> %acc, <32 x half> %a, <32 x hal
entry:
%0 = bitcast <32 x half> %a to <16 x float>
%1 = bitcast <32 x half> %b to <16 x float>
- %2 = tail call <16 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i16 -1, i32 4)
+ %2 = tail call contract <16 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i16 -1, i32 4)
%3 = bitcast <16 x float> %2 to <32 x half>
- %add.i = fadd <32 x half> %3, %acc
+ %add.i = fadd contract <32 x half> %3, %acc
ret <32 x half> %add.i
}
@@ -166,9 +166,9 @@ define dso_local <16 x half> @test15(<16 x half> %acc, <16 x half> %a, <16 x hal
entry:
%0 = bitcast <16 x half> %a to <8 x float>
%1 = bitcast <16 x half> %b to <8 x float>
- %2 = tail call <8 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i8 -1)
+ %2 = tail call contract <8 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i8 -1)
%3 = bitcast <8 x float> %2 to <16 x half>
- %add.i = fadd <16 x half> %3, %acc
+ %add.i = fadd contract <16 x half> %3, %acc
ret <16 x half> %add.i
}
@@ -180,9 +180,9 @@ define dso_local <16 x half> @test16(<16 x half> %acc, <16 x half> %a, <16 x hal
entry:
%0 = bitcast <16 x half> %a to <8 x float>
%1 = bitcast <16 x half> %b to <8 x float>
- %2 = tail call <8 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i8 -1)
+ %2 = tail call contract <8 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i8 -1)
%3 = bitcast <8 x float> %2 to <16 x half>
- %add.i = fadd <16 x half> %3, %acc
+ %add.i = fadd contract <16 x half> %3, %acc
ret <16 x half> %add.i
}
@@ -194,9 +194,9 @@ define dso_local <8 x half> @test17(<8 x half> %acc, <8 x half> %a, <8 x half> %
entry:
%0 = bitcast <8 x half> %a to <4 x float>
%1 = bitcast <8 x half> %b to <4 x float>
- %2 = tail call <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i8 -1)
+ %2 = tail call contract <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i8 -1)
%3 = bitcast <4 x float> %2 to <8 x half>
- %add.i = fadd <8 x half> %3, %acc
+ %add.i = fadd contract <8 x half> %3, %acc
ret <8 x half> %add.i
}
@@ -208,9 +208,9 @@ define dso_local <8 x half> @test18(<8 x half> %acc, <8 x half> %a, <8 x half> %
entry:
%0 = bitcast <8 x half> %a to <4 x float>
%1 = bitcast <8 x half> %b to <4 x float>
- %2 = tail call <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i8 -1)
+ %2 = tail call contract <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i8 -1)
%3 = bitcast <4 x float> %2 to <8 x half>
- %add.i = fadd <8 x half> %3, %acc
+ %add.i = fadd contract <8 x half> %3, %acc
ret <8 x half> %add.i
}
diff --git a/llvm/test/CodeGen/X86/avx512fp16-combine-vfmulc-fadd.ll b/llvm/test/CodeGen/X86/avx512fp16-combine-vfmulc-fadd.ll
index a509503584649..20df18c5a18b9 100644
--- a/llvm/test/CodeGen/X86/avx512fp16-combine-vfmulc-fadd.ll
+++ b/llvm/test/CodeGen/X86/avx512fp16-combine-vfmulc-fadd.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16,avx512vl --fp-contract=fast --enable-unsafe-fp-math | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16,avx512vl --enable-unsafe-fp-math | FileCheck %s
define dso_local <32 x half> @test1(<32 x half> %acc.coerce, <32 x half> %lhs.coerce, <32 x half> %rhs.coerce) {
; CHECK-LABEL: test1:
diff --git a/llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc-fadd.ll b/llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc-fadd.ll
index 43f30da15b20d..d96d7d1602040 100644
--- a/llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc-fadd.ll
+++ b/llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc-fadd.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16,avx512vl --fp-contract=fast --enable-unsafe-fp-math | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16,avx512vl --enable-unsafe-fp-math | FileCheck %s
define dso_local <32 x half> @test1(<32 x half> %acc.coerce, <32 x half> %lhs.coerce.conj, <32 x half> %rhs.coerce) local_unnamed_addr #0 {
; CHECK-LABEL: test1:
diff --git a/llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc.ll b/llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc.ll
index 7b142ea170c22..caf428a8c94d3 100644
--- a/llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc.ll
+++ b/llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16,avx512vl --fp-contract=fast --enable-unsafe-fp-math | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16,avx512vl --enable-unsafe-fp-math | FileCheck %s
define dso_local <32 x half> @test1(<32 x half> %lhs.coerce.conj, <32 x half> %rhs.coerce) local_unnamed_addr #0 {
; CHECK-LABEL: test1:
@@ -94,13 +94,13 @@ define dso_local <32 x half> @test6(<16 x i32> %a, <16 x float> %b) local_unname
entry:
%0 = xor <16 x i32> %a, splat (i32 -2147483648)
%1 = bitcast <16 x i32> %0 to <16 x float>
- %2 = tail call <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> splat (float 1.000000e+00), <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
+ %2 = tail call contract <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> splat (float 1.000000e+00), <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
%3 = bitcast <16 x float> %2 to <32 x half>
- %4 = tail call <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> %1, <16 x float> %b, <16 x float> zeroinitializer, i16 -1, i32 4)
+ %4 = tail call contract <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> %1, <16 x float> %b, <16 x float> zeroinitializer, i16 -1, i32 4)
%5 = bitcast <16 x float> %4 to <32 x half>
- %6 = fadd <32 x half> %3, %5
+ %6 = fadd contract <32 x half> %3, %5
%7 = bitcast <16 x float> %b to <32 x half>
- %8 = fadd <32 x half> %6, %7
+ %8 = fadd contract <32 x half> %6, %7
ret <32 x half> %8
}
diff --git a/llvm/test/CodeGen/X86/dag-combiner-fma-folding.ll b/llvm/test/CodeGen/X86/dag-combiner-fma-folding.ll
index 6291100f42c3d..c13b534b6881a 100644
--- a/llvm/test/CodeGen/X86/dag-combiner-fma-folding.ll
+++ b/llvm/test/CodeGen/X86/dag-combiner-fma-folding.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=x86_64-- --start-before=x86-isel -mattr=+avx,+fma %s -o - | FileCheck %s
-; RUN: llc -mtriple=x86_64-- --start-before=x86-isel -mattr=+avx,+fma %s -o - -fp-contract=fast | FileCheck %s
+; RUN: llc -mtriple=x86_64-- --start-before=x86-isel -mattr=+avx,+fma %s -o - | FileCheck %s
define double @fma_folding(double %x) {
; CHECK-LABEL: fma_folding:
diff --git a/llvm/test/CodeGen/X86/fma-do-not-commute.ll b/llvm/test/CodeGen/X86/fma-do-not-commute.ll
index 0dc8e62c56d0c..3009db2859dba 100644
--- a/llvm/test/CodeGen/X86/fma-do-not-commute.ll
+++ b/llvm/test/CodeGen/X86/fma-do-not-commute.ll
@@ -1,4 +1,4 @@
-; RUN: llc -fp-contract=fast -mattr=+fma -disable-cgp < %s -o - | FileCheck %s
+; RUN: llc -mattr=+fma -disable-cgp < %s -o - | FileCheck %s
; Check that the 2nd and 3rd arguments of fmaXXX231 reg1, reg2, mem3 are not commuted.
; <rdar://problem/16800495>
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
@@ -20,8 +20,8 @@ loop:
%sum0 = phi float [ %fma, %loop ], [ %arg, %entry ]
%addrVal = load float, ptr %addr, align 4
%addr2Val = load float, ptr %addr2, align 4
- %fmul = fmul float %addrVal, %addr2Val
- %fma = fadd float %sum0, %fmul
+ %fmul = fmul contract float %addrVal, %addr2Val
+ %fma = fadd contract float %sum0, %fmul
br i1 true, label %exit, label %loop
exit:
diff --git a/llvm/test/CodeGen/X86/fma_patterns.ll b/llvm/test/CodeGen/X86/fma_patterns.ll
index dc35c8f8dc657..8b409ba53b0fb 100644
--- a/llvm/test/CodeGen/X86/fma_patterns.ll
+++ b/llvm/test/CodeGen/X86/fma_patterns.ll
@@ -1,15 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma -fp-contract=fast | FileCheck %s --check-prefixes=FMA,FMA-INFS
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+fma -fp-contract=fast | FileCheck %s --check-prefixes=FMA4,FMA4-INFS
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4 -fp-contract=fast | FileCheck %s --check-prefixes=FMA4,FMA4-INFS
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl -fp-contract=fast | FileCheck %s --check-prefixes=AVX512,AVX512-INFS
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma -fp-contract=fast -enable-no-infs-fp-math | FileCheck %s --check-prefixes=FMA,FMA-NOINFS
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+fma -fp-contract=fast -enable-no-infs-fp-math | FileCheck %s --check-prefixes=FMA4,FMA4-NOINFS
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4 -fp-contract=fast -enable-no-infs-fp-math | FileCheck %s --check-prefixes=FMA4,FMA4-NOINFS
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl -fp-contract=fast -enable-no-infs-fp-math | FileCheck %s --check-prefixes=AVX512,AVX512-NOINFS
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma | FileCheck %s --check-prefixes=FMA,FMA-INFS
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+fma | FileCheck %s --check-prefixes=FMA4,FMA4-INFS
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4 | FileCheck %s --check-prefixes=FMA4,FMA4-INFS
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefixes=AVX512,AVX512-INFS
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma -enable-no-infs-fp-math | FileCheck %s --check-prefixes=FMA,FMA-NOINFS
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+fma -enable-no-infs-fp-math | FileCheck %s --check-prefixes=FMA4,FMA4-NOINFS
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4 -enable-no-infs-fp-math | FileCheck %s --check-prefixes=FMA4,FMA4-NOINFS
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl -enable-no-infs-fp-math | FileCheck %s --check-prefixes=AVX512,AVX512-NOINFS
;
-; Pattern: (fadd (fmul x, y), z) -> (fmadd x,y,z)
+; Pattern: (fadd contract (fmul contract x, y), z) -> (fmadd x,y,z)
;
define float @test_f32_fmadd(float %a0, float %a1, float %a2) {
@@ -27,8 +27,8 @@ define float @test_f32_fmadd(float %a0, float %a1, float %a2) {
; AVX512: # %bb.0:
; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
; AVX512-NEXT: retq
- %x = fmul float %a0, %a1
- %res = fadd float %x, %a2
+ %x = fmul contract float %a0, %a1
+ %res = fadd contract float %x, %a2
ret float %res
}
@@ -47,8 +47,8 @@ define <4 x float> @test_4f32_fmadd(<4 x float> %a0, <4 x float> %a1, <4 x float
; AVX512: # %bb.0:
; AVX512-NEXT: vfmadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
; AVX512-NEXT: retq
- %x = fmul <4 x float> %a0, %a1
- %res = fadd <4 x float> %x, %a2
+ %x = fmul contract <4 x float> %a0, %a1
+ %res = fadd contract <4 x float> %x, %a2
ret <4 x float> %res
}
@@ -67,8 +67,8 @@ define <8 x float> @test_8f32_fmadd(<8 x float> %a0, <8 x float> %a1, <8 x float
; AVX512: # %bb.0:
; AVX512-NEXT: vfmadd213ps {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm2
; AVX512-NEXT: retq
- %x = fmul <8 x float> %a0, %a1
- %res = fadd <8 x float> %x, %a2
+ %x = fmul contract <8 x float> %a0, %a1
+ %res = fadd contract <8 x float> %x, %a2
ret <8 x float> %res
}
@@ -87,8 +87,8 @@ define double @test_f64_fmadd(double %a0, double %a1, double %a2) {
; AVX512: # %bb.0:
; AVX512-NEXT: vfmadd213sd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
; AVX512-NEXT: retq
- %x = fmul double %a0, %a1
- %res = fadd double %x, %a2
+ %x = fmul contract double %a0, %a1
+ %res = fadd contract double %x, %a2
ret double %res
}
@@ -107,8 +107,8 @@ define <2 x double> @test_2f64_fmadd(<2 x double> %a0, <2 x double> %a1, <2 x do
; AVX512: # %bb.0:
; AVX512-NEXT: vfmadd213pd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
; AVX512-NEXT: retq
- %x = fmul <2 x double> %a0, %a1
- %res = fadd <2 x double> %x, %a2
+ %x = fmul contract <2 x double> %a0, %a1
+ %res = fadd contract <2 x double> %x, %a2
ret <2 x double> %res
}
@@ -127,13 +127,13 @@ define <4 x double> @test_4f64_fmadd(<4 x double> %a0, <4 x double> %a1, <4 x do
; AVX512: # %bb.0:
; AVX512-NEXT: vfmadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm2
; AVX512-NEXT: retq
- %x = fmul <4 x double> %a0, %a1
- %res = fadd <4 x double> %x, %a2
+ %x = fmul contract <4 x double> %a0, %a1
+ %res = fadd contract <4 x double> %x, %a2
ret <4 x double> %res
}
;
-; Pattern: (fsub (fmul x, y), z) -> (fmsub x, y, z)
+; Pattern: (fsub contract (fmul contract x, y), z) -> (fmsub x, y, z)
;
define float @test_f32_fmsub(float %a0, float %a1, float %a2) {
@@ -151,8 +151,8 @@ define float @test_f32_fmsub(float %a0, float %a1, float %a2) {
; AVX512: # %bb.0:
; AVX512-NEXT: vfmsub213ss {{.*#+}} xmm0 = (xmm1 * xmm0) - xmm2
; AVX512-NEXT: retq
- %x = fmul float %a0, %a1
- %res = fsub float %x, %a2
+ %x = fmul contract float %a0, %a1
+ %res = fsub contract float %x, %a2
ret float %res
}
@@ -171,8 +171,8 @@ define <4 x float> @test_4f32_fmsub(<4 x float> %a0, <4 x float> %a1, <4 x float
; AVX512: # %bb.0:
; AVX512-NEXT: vfmsub213ps {{.*#+}} xmm0 = (xmm1 * xmm0) - xmm2
; AVX512-NEXT: retq
- %x = fmul <4 x float> %a0, %a1
- %res = fsub <4 x float> %x, %a2
+ %x = fmul contract <4 x float> %a0, %a1
+ %res = fsub contract <4 x float> %x, %a2
ret <4 x float> %res
}
@@ -191,8 +191,8 @@ define <8 x float> @test_8f32_fmsub(<8 x float> %a0, <8 x float> %a1, <8 x float
; AVX512: # %bb.0:
; AVX512-NEXT: vfmsub213ps {{.*#+}} ymm0 = (ymm1 * ymm0) - ymm2
; AVX512-NEXT: retq
- %x = fmul <8 x float> %a0, %a1
- %res = fsub <8 x float> %x, %a2
+ %x = fmul contract <8 x float> %a0, %a1
+ %res = fsub contract <8 x float> %x, %a2
ret <8 x float> %res
}
@@ -211,8 +211,8 @@ define double @test_f64_fmsub(double %a0, double %a1, double %a2) {
; AVX512: # %bb.0:
; AVX512-NEXT: vfmsub213sd {{.*#+}} xmm0 = (xmm1 * xmm0) - xmm2
; AVX512-NEXT: retq
- %x = fmul double %a0, %a1
- %res = fsub double %x, %a2
+ %x = fmul contract double %a0, %a1
+ %res = fsub contract double %x, %a2
ret double %res
}
@@ -231,8 +231,8 @@ define <2 x double> @test_2f64_fmsub(<2 x double> %a0, <2 x double> %a1, <2 x do
; AVX512: # %bb.0:
; AVX512-NEXT: vfmsub213pd {{.*#+}} xmm0 = (xmm1 * xmm0) - xmm2
; AVX512-NEXT: retq
- %x = fmul <2 x double> %a0, %a1
- %res = fsub <2 x double> %x, %a2
+ %x = fmul contract <2 x double> %a0, %a1
+ %res = fsub contract <2 x double> %x, %a2
ret <2 x double> %res
}
@@ -251,13 +251,13 @@ define <4 x double> @test_4f64_fmsub(<4 x double> %a0, <4 x double> %a1, <4 x do
; AVX512: # %bb.0:
; AVX512-NEXT: vfmsub213pd {{.*#+}} ymm0 = (ymm1 * ymm0) - ymm2
; AVX512-NEXT: retq
- %x = fmul <4 x double> %a0, %a1
- %res = fsub <4 x double> %x, %a2
+ %x = fmul contract <4 x double> %a0, %a1
+ %res = fsub contract <4 x double> %x, %a2
ret <4 x double> %res
}
;
-; Pattern: (fsub z, (fmul x, y)) -> (fnmadd x, y, z)
+; Pattern: (fsub contract z, (fmul contract x, y)) -> (fnmadd x, y, z)
;
define float @test_f32_fnmadd(float %a0, float %a1, float %a2) {
@@ -275,8 +275,8 @@ define float @test_f32_fnmadd(float %a0, float %a1, float %a2) {
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmadd213ss {{.*#+}} xmm0 = -(xmm1 * xmm0) + xmm2
; AVX512-NEXT: retq
- %x = fmul float %a0, %a1
- %res = fsub float %a2, %x
+ %x = fmul contract float %a0, %a1
+ %res = fsub contract float %a2, %x
ret float %res
}
@@ -295,8 +295,8 @@ define <4 x float> @test_4f32_fnmadd(<4 x float> %a0, <4 x float> %a1, <4 x floa
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmadd213ps {{.*#+}} xmm0 = -(xmm1 * xmm0) + xmm2
; AVX512-NEXT: retq
- %x = fmul <4 x float> %a0, %a1
- %res = fsub <4 x float> %a2, %x
+ %x = fmul contract <4 x float> %a0, %a1
+ %res = fsub contract <4 x float> %a2, %x
ret <4 x float> %res
}
@@ -315,8 +315,8 @@ define <8 x float> @test_8f32_fnmadd(<8 x float> %a0, <8 x float> %a1, <8 x floa
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmadd213ps {{.*#+}} ymm0 = -(ymm1 * ymm0) + ymm2
; AVX512-NEXT: retq
- %x = fmul <8 x float> %a0, %a1
- %res = fsub <8 x float> %a2, %x
+ %x = fmul contract <8 x float> %a0, %a1
+ %res = fsub contract <8 x float> %a2, %x
ret <8 x float> %res
}
@@ -335,8 +335,8 @@ define double @test_f64_fnmadd(double %a0, double %a1, double %a2) {
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmadd213sd {{.*#+}} xmm0 = -(xmm1 * xmm0) + xmm2
; AVX512-NEXT: retq
- %x = fmul double %a0, %a1
- %res = fsub double %a2, %x
+ %x = fmul contract double %a0, %a1
+ %res = fsub contract double %a2, %x
ret double %res
}
@@ -355,8 +355,8 @@ define <2 x double> @test_2f64_fnmadd(<2 x double> %a0, <2 x double> %a1, <2 x d
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmadd213pd {{.*#+}} xmm0 = -(xmm1 * xmm0) + xmm2
; AVX512-NEXT: retq
- %x = fmul <2 x double> %a0, %a1
- %res = fsub <2 x double> %a2, %x
+ %x = fmul contract <2 x double> %a0, %a1
+ %res = fsub contract <2 x double> %a2, %x
ret <2 x double> %res
}
@@ -375,13 +375,13 @@ define <4 x double> @test_4f64_fnmadd(<4 x double> %a0, <4 x double> %a1, <4 x d
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmadd213pd {{.*#+}} ymm0 = -(ymm1 * ymm0) + ymm2
; AVX512-NEXT: retq
- %x = fmul <4 x double> %a0, %a1
- %res = fsub <4 x double> %a2, %x
+ %x = fmul contract <4 x double> %a0, %a1
+ %res = fsub contract <4 x double> %a2, %x
ret <4 x double> %res
}
;
-; Pattern: (fsub (fneg (fmul x, y)), z) -> (fnmsub x, y, z)
+; Pattern: (fsub contract (fneg (fmul contract x, y)), z) -> (fnmsub x, y, z)
;
define float @test_f32_fnmsub(float %a0, float %a1, float %a2) {
@@ -399,9 +399,9 @@ define float @test_f32_fnmsub(float %a0, float %a1, float %a2) {
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmsub213ss {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm2
; AVX512-NEXT: retq
- %x = fmul float %a0, %a1
- %y = fsub float -0.000000e+00, %x
- %res = fsub float %y, %a2
+ %x = fmul contract float %a0, %a1
+ %y = fsub contract float -0.000000e+00, %x
+ %res = fsub contract float %y, %a2
ret float %res
}
@@ -420,9 +420,9 @@ define <4 x float> @test_4f32_fnmsub(<4 x float> %a0, <4 x float> %a1, <4 x floa
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmsub213ps {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm2
; AVX512-NEXT: retq
- %x = fmul <4 x float> %a0, %a1
- %y = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x
- %res = fsub <4 x float> %y, %a2
+ %x = fmul contract <4 x float> %a0, %a1
+ %y = fsub contract <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x
+ %res = fsub contract <4 x float> %y, %a2
ret <4 x float> %res
}
@@ -441,9 +441,9 @@ define <8 x float> @test_8f32_fnmsub(<8 x float> %a0, <8 x float> %a1, <8 x floa
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmsub213ps {{.*#+}} ymm0 = -(ymm1 * ymm0) - ymm2
; AVX512-NEXT: retq
- %x = fmul <8 x float> %a0, %a1
- %y = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x
- %res = fsub <8 x float> %y, %a2
+ %x = fmul contract <8 x float> %a0, %a1
+ %y = fsub contract <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x
+ %res = fsub contract <8 x float> %y, %a2
ret <8 x float> %res
}
@@ -462,9 +462,9 @@ define double @test_f64_fnmsub(double %a0, double %a1, double %a2) {
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmsub213sd {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm2
; AVX512-NEXT: retq
- %x = fmul double %a0, %a1
- %y = fsub double -0.000000e+00, %x
- %res = fsub double %y, %a2
+ %x = fmul contract double %a0, %a1
+ %y = fsub contract double -0.000000e+00, %x
+ %res = fsub contract double %y, %a2
ret double %res
}
@@ -483,9 +483,9 @@ define <2 x double> @test_2f64_fnmsub(<2 x double> %a0, <2 x double> %a1, <2 x d
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmsub213pd {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm2
; AVX512-NEXT: retq
- %x = fmul <2 x double> %a0, %a1
- %y = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %x
- %res = fsub <2 x double> %y, %a2
+ %x = fmul contract <2 x double> %a0, %a1
+ %y = fsub contract <2 x double> <double -0.000000e+00, double -0.000000e+00>, %x
+ %res = fsub contract <2 x double> %y, %a2
ret <2 x double> %res
}
@@ -504,9 +504,9 @@ define <4 x double> @test_4f64_fnmsub(<4 x double> %a0, <4 x double> %a1, <4 x d
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmsub213pd {{.*#+}} ymm0 = -(ymm1 * ymm0) - ymm2
; AVX512-NEXT: retq
- %x = fmul <4 x double> %a0, %a1
- %y = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %x
- %res = fsub <4 x double> %y, %a2
+ %x = fmul contract <4 x double> %a0, %a1
+ %y = fsub contract <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %x
+ %res = fsub contract <4 x double> %y, %a2
ret <4 x double> %res
}
@@ -530,8 +530,8 @@ define <4 x float> @test_4f32_fmadd_load(ptr %a0, <4 x float> %a1, <4 x float> %
; AVX512-NEXT: vfmadd132ps {{.*#+}} xmm0 = (xmm0 * mem) + xmm1
; AVX512-NEXT: retq
%x = load <4 x float>, ptr %a0
- %y = fmul <4 x float> %x, %a1
- %res = fadd <4 x float> %y, %a2
+ %y = fmul contract <4 x float> %x, %a1
+ %res = fadd contract <4 x float> %y, %a2
ret <4 x float> %res
}
@@ -551,8 +551,8 @@ define <2 x double> @test_2f64_fmsub_load(ptr %a0, <2 x double> %a1, <2 x double
; AVX512-NEXT: vfmsub132pd {{.*#+}} xmm0 = (xmm0 * mem) - xmm1
; AVX512-NEXT: retq
%x = load <2 x double>, ptr %a0
- %y = fmul <2 x double> %x, %a1
- %res = fsub <2 x double> %y, %a2
+ %y = fmul contract <2 x double> %x, %a1
+ %res = fsub contract <2 x double> %y, %a2
ret <2 x double> %res
}
@@ -593,8 +593,8 @@ define <4 x float> @test_v4f32_mul_add_x_one_y(<4 x float> %x, <4 x float> %y) {
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm1
; AVX512-NOINFS-NEXT: retq
- %a = fadd <4 x float> %x, <float 1.0, float 1.0, float 1.0, float 1.0>
- %m = fmul <4 x float> %a, %y
+ %a = fadd contract <4 x float> %x, <float 1.0, float 1.0, float 1.0, float 1.0>
+ %m = fmul contract <4 x float> %a, %y
ret <4 x float> %m
}
@@ -631,8 +631,8 @@ define <4 x float> @test_v4f32_mul_y_add_x_one(<4 x float> %x, <4 x float> %y) {
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm1
; AVX512-NOINFS-NEXT: retq
- %a = fadd <4 x float> %x, <float 1.0, float 1.0, float 1.0, float 1.0>
- %m = fmul <4 x float> %y, %a
+ %a = fadd contract <4 x float> %x, <float 1.0, float 1.0, float 1.0, float 1.0>
+ %m = fmul contract <4 x float> %y, %a
ret <4 x float> %m
}
@@ -669,8 +669,8 @@ define <4 x float> @test_v4f32_mul_y_add_x_one_undefs(<4 x float> %x, <4 x float
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm1
; AVX512-NOINFS-NEXT: retq
- %a = fadd <4 x float> %x, <float 1.0, float undef, float 1.0, float undef>
- %m = fmul <4 x float> %y, %a
+ %a = fadd contract <4 x float> %x, <float 1.0, float undef, float 1.0, float undef>
+ %m = fmul contract <4 x float> %y, %a
ret <4 x float> %m
}
@@ -707,8 +707,8 @@ define <4 x float> @test_v4f32_mul_add_x_negone_y(<4 x float> %x, <4 x float> %y
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmsub213ps {{.*#+}} xmm0 = (xmm1 * xmm0) - xmm1
; AVX512-NOINFS-NEXT: retq
- %a = fadd <4 x float> %x, <float -1.0, float -1.0, float -1.0, float -1.0>
- %m = fmul <4 x float> %a, %y
+ %a = fadd contract <4 x float> %x, <float -1.0, float -1.0, float -1.0, float -1.0>
+ %m = fmul contract <4 x float> %a, %y
ret <4 x float> %m
}
@@ -745,8 +745,8 @@ define <4 x float> @test_v4f32_mul_y_add_x_negone(<4 x float> %x, <4 x float> %y
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmsub213ps {{.*#+}} xmm0 = (xmm1 * xmm0) - xmm1
; AVX512-NOINFS-NEXT: retq
- %a = fadd <4 x float> %x, <float -1.0, float -1.0, float -1.0, float -1.0>
- %m = fmul <4 x float> %y, %a
+ %a = fadd contract <4 x float> %x, <float -1.0, float -1.0, float -1.0, float -1.0>
+ %m = fmul contract <4 x float> %y, %a
ret <4 x float> %m
}
@@ -783,8 +783,8 @@ define <4 x float> @test_v4f32_mul_y_add_x_negone_undefs(<4 x float> %x, <4 x fl
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmsub213ps {{.*#+}} xmm0 = (xmm1 * xmm0) - xmm1
; AVX512-NOINFS-NEXT: retq
- %a = fadd <4 x float> %x, <float undef, float -1.0, float undef, float -1.0>
- %m = fmul <4 x float> %y, %a
+ %a = fadd contract <4 x float> %x, <float undef, float -1.0, float undef, float -1.0>
+ %m = fmul contract <4 x float> %y, %a
ret <4 x float> %m
}
@@ -824,8 +824,8 @@ define <4 x float> @test_v4f32_mul_sub_one_x_y(<4 x float> %x, <4 x float> %y) {
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfnmadd213ps {{.*#+}} xmm0 = -(xmm1 * xmm0) + xmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %x
- %m = fmul <4 x float> %s, %y
+ %s = fsub contract <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %x
+ %m = fmul contract <4 x float> %s, %y
ret <4 x float> %m
}
@@ -865,8 +865,8 @@ define <4 x float> @test_v4f32_mul_y_sub_one_x(<4 x float> %x, <4 x float> %y) {
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfnmadd213ps {{.*#+}} xmm0 = -(xmm1 * xmm0) + xmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %x
- %m = fmul <4 x float> %y, %s
+ %s = fsub contract <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %x
+ %m = fmul contract <4 x float> %y, %s
ret <4 x float> %m
}
@@ -906,8 +906,8 @@ define <4 x float> @test_v4f32_mul_y_sub_one_x_undefs(<4 x float> %x, <4 x float
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfnmadd213ps {{.*#+}} xmm0 = -(xmm1 * xmm0) + xmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <4 x float> <float 1.0, float undef, float 1.0, float 1.0>, %x
- %m = fmul <4 x float> %y, %s
+ %s = fsub contract <4 x float> <float 1.0, float undef, float 1.0, float 1.0>, %x
+ %m = fmul contract <4 x float> %y, %s
ret <4 x float> %m
}
@@ -947,8 +947,8 @@ define <4 x float> @test_v4f32_mul_sub_negone_x_y(<4 x float> %x, <4 x float> %y
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfnmsub213ps {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <4 x float> <float -1.0, float -1.0, float -1.0, float -1.0>, %x
- %m = fmul <4 x float> %s, %y
+ %s = fsub contract <4 x float> <float -1.0, float -1.0, float -1.0, float -1.0>, %x
+ %m = fmul contract <4 x float> %s, %y
ret <4 x float> %m
}
@@ -988,8 +988,8 @@ define <4 x float> @test_v4f32_mul_y_sub_negone_x(<4 x float> %x, <4 x float> %y
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfnmsub213ps {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <4 x float> <float -1.0, float -1.0, float -1.0, float -1.0>, %x
- %m = fmul <4 x float> %y, %s
+ %s = fsub contract <4 x float> <float -1.0, float -1.0, float -1.0, float -1.0>, %x
+ %m = fmul contract <4 x float> %y, %s
ret <4 x float> %m
}
@@ -1029,8 +1029,8 @@ define <4 x float> @test_v4f32_mul_y_sub_negone_x_undefs(<4 x float> %x, <4 x fl
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfnmsub213ps {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <4 x float> <float -1.0, float -1.0, float undef, float -1.0>, %x
- %m = fmul <4 x float> %y, %s
+ %s = fsub contract <4 x float> <float -1.0, float -1.0, float undef, float -1.0>, %x
+ %m = fmul contract <4 x float> %y, %s
ret <4 x float> %m
}
@@ -1067,8 +1067,8 @@ define <4 x float> @test_v4f32_mul_sub_x_one_y(<4 x float> %x, <4 x float> %y) {
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmsub213ps {{.*#+}} xmm0 = (xmm1 * xmm0) - xmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <4 x float> %x, <float 1.0, float 1.0, float 1.0, float 1.0>
- %m = fmul <4 x float> %s, %y
+ %s = fsub contract <4 x float> %x, <float 1.0, float 1.0, float 1.0, float 1.0>
+ %m = fmul contract <4 x float> %s, %y
ret <4 x float> %m
}
@@ -1105,8 +1105,8 @@ define <4 x float> @test_v4f32_mul_y_sub_x_one(<4 x float> %x, <4 x float> %y) {
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmsub213ps {{.*#+}} xmm0 = (xmm1 * xmm0) - xmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <4 x float> %x, <float 1.0, float 1.0, float 1.0, float 1.0>
- %m = fmul <4 x float> %y, %s
+ %s = fsub contract <4 x float> %x, <float 1.0, float 1.0, float 1.0, float 1.0>
+ %m = fmul contract <4 x float> %y, %s
ret <4 x float> %m
}
@@ -1143,8 +1143,8 @@ define <4 x float> @test_v4f32_mul_y_sub_x_one_undefs(<4 x float> %x, <4 x float
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmsub213ps {{.*#+}} xmm0 = (xmm1 * xmm0) - xmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <4 x float> %x, <float 1.0, float 1.0, float 1.0, float undef>
- %m = fmul <4 x float> %y, %s
+ %s = fsub contract <4 x float> %x, <float 1.0, float 1.0, float 1.0, float undef>
+ %m = fmul contract <4 x float> %y, %s
ret <4 x float> %m
}
@@ -1181,8 +1181,8 @@ define <4 x float> @test_v4f32_mul_sub_x_negone_y(<4 x float> %x, <4 x float> %y
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <4 x float> %x, <float -1.0, float -1.0, float -1.0, float -1.0>
- %m = fmul <4 x float> %s, %y
+ %s = fsub contract <4 x float> %x, <float -1.0, float -1.0, float -1.0, float -1.0>
+ %m = fmul contract <4 x float> %s, %y
ret <4 x float> %m
}
@@ -1219,8 +1219,8 @@ define <4 x float> @test_v4f32_mul_y_sub_x_negone(<4 x float> %x, <4 x float> %y
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <4 x float> %x, <float -1.0, float -1.0, float -1.0, float -1.0>
- %m = fmul <4 x float> %y, %s
+ %s = fsub contract <4 x float> %x, <float -1.0, float -1.0, float -1.0, float -1.0>
+ %m = fmul contract <4 x float> %y, %s
ret <4 x float> %m
}
@@ -1257,8 +1257,8 @@ define <4 x float> @test_v4f32_mul_y_sub_x_negone_undefs(<4 x float> %x, <4 x fl
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <4 x float> %x, <float undef, float -1.0, float -1.0, float -1.0>
- %m = fmul <4 x float> %y, %s
+ %s = fsub contract <4 x float> %x, <float undef, float -1.0, float -1.0, float -1.0>
+ %m = fmul contract <4 x float> %y, %s
ret <4 x float> %m
}
@@ -1308,10 +1308,10 @@ define float @test_f32_interp(float %x, float %y, float %t) {
; AVX512-NOINFS-NEXT: vfmsub213ss {{.*#+}} xmm1 = (xmm2 * xmm1) - xmm1
; AVX512-NOINFS-NEXT: vfmsub213ss {{.*#+}} xmm0 = (xmm2 * xmm0) - xmm1
; AVX512-NOINFS-NEXT: retq
- %t1 = fsub nsz float 1.0, %t
- %tx = fmul nsz float %x, %t
- %ty = fmul nsz float %y, %t1
- %r = fadd nsz float %tx, %ty
+ %t1 = fsub contract nsz float 1.0, %t
+ %tx = fmul contract nsz float %x, %t
+ %ty = fmul contract nsz float %y, %t1
+ %r = fadd contract nsz float %tx, %ty
ret float %r
}
@@ -1357,10 +1357,10 @@ define <4 x float> @test_v4f32_interp(<4 x float> %x, <4 x float> %y, <4 x float
; AVX512-NOINFS-NEXT: vfmsub213ps {{.*#+}} xmm1 = (xmm2 * xmm1) - xmm1
; AVX512-NOINFS-NEXT: vfmsub213ps {{.*#+}} xmm0 = (xmm2 * xmm0) - xmm1
; AVX512-NOINFS-NEXT: retq
- %t1 = fsub nsz <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %t
- %tx = fmul nsz <4 x float> %x, %t
- %ty = fmul nsz <4 x float> %y, %t1
- %r = fadd nsz <4 x float> %tx, %ty
+ %t1 = fsub contract nsz <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %t
+ %tx = fmul contract nsz <4 x float> %x, %t
+ %ty = fmul contract nsz <4 x float> %y, %t1
+ %r = fadd contract nsz <4 x float> %tx, %ty
ret <4 x float> %r
}
@@ -1406,10 +1406,10 @@ define <8 x float> @test_v8f32_interp(<8 x float> %x, <8 x float> %y, <8 x float
; AVX512-NOINFS-NEXT: vfmsub213ps {{.*#+}} ymm1 = (ymm2 * ymm1) - ymm1
; AVX512-NOINFS-NEXT: vfmsub213ps {{.*#+}} ymm0 = (ymm2 * ymm0) - ymm1
; AVX512-NOINFS-NEXT: retq
- %t1 = fsub nsz <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %t
- %tx = fmul nsz <8 x float> %x, %t
- %ty = fmul nsz <8 x float> %y, %t1
- %r = fadd nsz <8 x float> %tx, %ty
+ %t1 = fsub contract nsz <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %t
+ %tx = fmul contract nsz <8 x float> %x, %t
+ %ty = fmul contract nsz <8 x float> %y, %t1
+ %r = fadd contract nsz <8 x float> %tx, %ty
ret <8 x float> %r
}
@@ -1455,10 +1455,10 @@ define double @test_f64_interp(double %x, double %y, double %t) {
; AVX512-NOINFS-NEXT: vfmsub213sd {{.*#+}} xmm1 = (xmm2 * xmm1) - xmm1
; AVX512-NOINFS-NEXT: vfmsub213sd {{.*#+}} xmm0 = (xmm2 * xmm0) - xmm1
; AVX512-NOINFS-NEXT: retq
- %t1 = fsub nsz double 1.0, %t
- %tx = fmul nsz double %x, %t
- %ty = fmul nsz double %y, %t1
- %r = fadd nsz double %tx, %ty
+ %t1 = fsub contract nsz double 1.0, %t
+ %tx = fmul contract nsz double %x, %t
+ %ty = fmul contract nsz double %y, %t1
+ %r = fadd contract nsz double %tx, %ty
ret double %r
}
@@ -1507,10 +1507,10 @@ define <2 x double> @test_v2f64_interp(<2 x double> %x, <2 x double> %y, <2 x do
; AVX512-NOINFS-NEXT: vfmsub213pd {{.*#+}} xmm1 = (xmm2 * xmm1) - xmm1
; AVX512-NOINFS-NEXT: vfmsub213pd {{.*#+}} xmm0 = (xmm2 * xmm0) - xmm1
; AVX512-NOINFS-NEXT: retq
- %t1 = fsub nsz <2 x double> <double 1.0, double 1.0>, %t
- %tx = fmul nsz <2 x double> %x, %t
- %ty = fmul nsz <2 x double> %y, %t1
- %r = fadd nsz <2 x double> %tx, %ty
+ %t1 = fsub contract nsz <2 x double> <double 1.0, double 1.0>, %t
+ %tx = fmul contract nsz <2 x double> %x, %t
+ %ty = fmul contract nsz <2 x double> %y, %t1
+ %r = fadd contract nsz <2 x double> %tx, %ty
ret <2 x double> %r
}
@@ -1556,10 +1556,10 @@ define <4 x double> @test_v4f64_interp(<4 x double> %x, <4 x double> %y, <4 x do
; AVX512-NOINFS-NEXT: vfmsub213pd {{.*#+}} ymm1 = (ymm2 * ymm1) - ymm1
; AVX512-NOINFS-NEXT: vfmsub213pd {{.*#+}} ymm0 = (ymm2 * ymm0) - ymm1
; AVX512-NOINFS-NEXT: retq
- %t1 = fsub nsz <4 x double> <double 1.0, double 1.0, double 1.0, double 1.0>, %t
- %tx = fmul nsz <4 x double> %x, %t
- %ty = fmul nsz <4 x double> %y, %t1
- %r = fadd nsz <4 x double> %tx, %ty
+ %t1 = fsub contract nsz <4 x double> <double 1.0, double 1.0, double 1.0, double 1.0>, %t
+ %tx = fmul contract nsz <4 x double> %x, %t
+ %ty = fmul contract nsz <4 x double> %y, %t1
+ %r = fadd contract nsz <4 x double> %tx, %ty
ret <4 x double> %r
}
@@ -1582,9 +1582,9 @@ define <4 x float> @test_v4f32_fneg_fmadd(<4 x float> %a0, <4 x float> %a1, <4 x
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmsub213ps {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm2
; AVX512-NEXT: retq
- %mul = fmul contract nsz <4 x float> %a0, %a1
- %add = fadd contract nsz <4 x float> %mul, %a2
- %neg = fsub contract nsz <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %add
+ %mul = fmul contract contract nsz <4 x float> %a0, %a1
+ %add = fadd contract contract nsz <4 x float> %mul, %a2
+ %neg = fsub contract contract nsz <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %add
ret <4 x float> %neg
}
@@ -1603,9 +1603,9 @@ define <4 x double> @test_v4f64_fneg_fmsub(<4 x double> %a0, <4 x double> %a1, <
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmadd213pd {{.*#+}} ymm0 = -(ymm1 * ymm0) + ymm2
; AVX512-NEXT: retq
- %mul = fmul nsz <4 x double> %a0, %a1
- %sub = fsub nsz <4 x double> %mul, %a2
- %neg = fsub nsz <4 x double> <double -0.0, double -0.0, double -0.0, double -0.0>, %sub
+ %mul = fmul contract nsz <4 x double> %a0, %a1
+ %sub = fsub contract nsz <4 x double> %mul, %a2
+ %neg = fsub contract nsz <4 x double> <double -0.0, double -0.0, double -0.0, double -0.0>, %sub
ret <4 x double> %neg
}
@@ -1624,10 +1624,10 @@ define <4 x float> @test_v4f32_fneg_fnmadd(<4 x float> %a0, <4 x float> %a1, <4
; AVX512: # %bb.0:
; AVX512-NEXT: vfmsub213ps {{.*#+}} xmm0 = (xmm1 * xmm0) - xmm2
; AVX512-NEXT: retq
- %mul = fmul contract nsz <4 x float> %a0, %a1
- %neg0 = fsub contract nsz <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %mul
- %add = fadd contract nsz <4 x float> %neg0, %a2
- %neg1 = fsub contract nsz <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %add
+ %mul = fmul contract contract nsz <4 x float> %a0, %a1
+ %neg0 = fsub contract contract nsz <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %mul
+ %add = fadd contract contract nsz <4 x float> %neg0, %a2
+ %neg1 = fsub contract contract nsz <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %add
ret <4 x float> %neg1
}
@@ -1646,15 +1646,15 @@ define <4 x double> @test_v4f64_fneg_fnmsub(<4 x double> %a0, <4 x double> %a1,
; AVX512: # %bb.0:
; AVX512-NEXT: vfmadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm2
; AVX512-NEXT: retq
- %mul = fmul contract nsz <4 x double> %a0, %a1
- %neg0 = fsub contract nsz <4 x double> <double -0.0, double -0.0, double -0.0, double -0.0>, %mul
- %sub = fsub contract nsz <4 x double> %neg0, %a2
- %neg1 = fsub contract nsz <4 x double> <double -0.0, double -0.0, double -0.0, double -0.0>, %sub
+ %mul = fmul contract contract nsz <4 x double> %a0, %a1
+ %neg0 = fsub contract contract nsz <4 x double> <double -0.0, double -0.0, double -0.0, double -0.0>, %mul
+ %sub = fsub contract contract nsz <4 x double> %neg0, %a2
+ %neg1 = fsub contract contract nsz <4 x double> <double -0.0, double -0.0, double -0.0, double -0.0>, %sub
ret <4 x double> %neg1
}
;
-; Pattern: (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
+; Pattern: (fma x, c1, (fmul contract x, c2)) -> (fmul contract x, c1+c2)
;
define <4 x float> @test_v4f32_fma_x_c1_fmul_x_c2(<4 x float> %x) {
@@ -1672,14 +1672,14 @@ define <4 x float> @test_v4f32_fma_x_c1_fmul_x_c2(<4 x float> %x) {
; AVX512: # %bb.0:
; AVX512-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
; AVX512-NEXT: retq
- %m0 = fmul contract reassoc <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>
- %m1 = fmul contract reassoc <4 x float> %x, <float 4.0, float 3.0, float 2.0, float 1.0>
- %a = fadd contract reassoc <4 x float> %m0, %m1
+ %m0 = fmul contract contract reassoc <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>
+ %m1 = fmul contract contract reassoc <4 x float> %x, <float 4.0, float 3.0, float 2.0, float 1.0>
+ %a = fadd contract contract reassoc <4 x float> %m0, %m1
ret <4 x float> %a
}
;
-; Pattern: (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)
+; Pattern: (fma (fmul contract x, c1), c2, y) -> (fma x, c1*c2, y)
;
define <4 x float> @test_v4f32_fma_fmul_x_c1_c2_y(<4 x float> %x, <4 x float> %y) {
@@ -1697,13 +1697,13 @@ define <4 x float> @test_v4f32_fma_fmul_x_c1_c2_y(<4 x float> %x, <4 x float> %y
; AVX512: # %bb.0:
; AVX512-NEXT: vfmadd132ps {{.*#+}} xmm0 = (xmm0 * mem) + xmm1
; AVX512-NEXT: retq
- %m0 = fmul contract reassoc <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>
- %m1 = fmul contract reassoc <4 x float> %m0, <float 4.0, float 3.0, float 2.0, float 1.0>
- %a = fadd contract reassoc <4 x float> %m1, %y
+ %m0 = fmul contract contract reassoc <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>
+ %m1 = fmul contract contract reassoc <4 x float> %m0, <float 4.0, float 3.0, float 2.0, float 1.0>
+ %a = fadd contract contract reassoc <4 x float> %m1, %y
ret <4 x float> %a
}
-; Pattern: (fneg (fmul x, y)) -> (fnmsub x, y, 0)
+; Pattern: (fneg (fmul contract x, y)) -> (fnmsub x, y, 0)
define double @test_f64_fneg_fmul(double %x, double %y) {
; FMA-LABEL: test_f64_fneg_fmul:
@@ -1723,8 +1723,8 @@ define double @test_f64_fneg_fmul(double %x, double %y) {
; AVX512-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; AVX512-NEXT: vfnmsub213sd {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm2
; AVX512-NEXT: retq
- %m = fmul contract nsz double %x, %y
- %n = fsub contract double -0.0, %m
+ %m = fmul contract contract nsz double %x, %y
+ %n = fsub contract contract double -0.0, %m
ret double %n
}
@@ -1746,8 +1746,8 @@ define <4 x float> @test_v4f32_fneg_fmul(<4 x float> %x, <4 x float> %y) {
; AVX512-NEXT: vxorps %xmm2, %xmm2, %xmm2
; AVX512-NEXT: vfnmsub213ps {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm2
; AVX512-NEXT: retq
- %m = fmul contract nsz <4 x float> %x, %y
- %n = fsub contract <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %m
+ %m = fmul contract contract nsz <4 x float> %x, %y
+ %n = fsub contract contract <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %m
ret <4 x float> %n
}
@@ -1769,8 +1769,8 @@ define <4 x double> @test_v4f64_fneg_fmul(<4 x double> %x, <4 x double> %y) {
; AVX512-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; AVX512-NEXT: vfnmsub213pd {{.*#+}} ymm0 = -(ymm1 * ymm0) - ymm2
; AVX512-NEXT: retq
- %m = fmul contract nsz <4 x double> %x, %y
- %n = fsub contract <4 x double> <double -0.0, double -0.0, double -0.0, double -0.0>, %m
+ %m = fmul contract contract nsz <4 x double> %x, %y
+ %n = fsub contract contract <4 x double> <double -0.0, double -0.0, double -0.0, double -0.0>, %m
ret <4 x double> %n
}
@@ -1792,8 +1792,8 @@ define <4 x double> @test_v4f64_fneg_fmul_no_nsz(<4 x double> %x, <4 x double> %
; AVX512-NEXT: vmulpd %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; AVX512-NEXT: retq
- %m = fmul contract <4 x double> %x, %y
- %n = fsub contract <4 x double> <double -0.0, double -0.0, double -0.0, double -0.0>, %m
+ %m = fmul contract contract <4 x double> %x, %y
+ %n = fsub contract contract <4 x double> <double -0.0, double -0.0, double -0.0, double -0.0>, %m
ret <4 x double> %n
}
@@ -1817,15 +1817,15 @@ define double @fadd_fma_fmul_1(double %a, double %b, double %c, double %d, doubl
; AVX512-NEXT: vfmadd213sd {{.*#+}} xmm2 = (xmm3 * xmm2) + xmm4
; AVX512-NEXT: vfmadd213sd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
; AVX512-NEXT: retq
- %m1 = fmul fast double %a, %b
- %m2 = fmul fast double %c, %d
- %a1 = fadd fast double %m1, %m2
- %a2 = fadd fast double %a1, %n1
+ %m1 = fmul contract fast double %a, %b
+ %m2 = fmul contract fast double %c, %d
+ %a1 = fadd contract fast double %m1, %m2
+ %a2 = fadd contract fast double %a1, %n1
ret double %a2
}
-; Minimum FMF - the 1st fadd is contracted because that combines
-; fmul+fadd as specified by the order of operations; the 2nd fadd
+; Minimum FMF - the 1st fadd contract is contracted because that combines
+; fmul contract+fadd contract as specified by the order of operations; the 2nd fadd contract
; requires reassociation to fuse with c*d.
define float @fadd_fma_fmul_fmf(float %a, float %b, float %c, float %d, float %n0) nounwind {
@@ -1846,10 +1846,10 @@ define float @fadd_fma_fmul_fmf(float %a, float %b, float %c, float %d, float %n
; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm2 = (xmm3 * xmm2) + xmm4
; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
; AVX512-NEXT: retq
- %m1 = fmul float %a, %b
- %m2 = fmul float %c, %d
- %a1 = fadd contract float %m1, %m2
- %a2 = fadd reassoc float %n0, %a1
+ %m1 = fmul contract float %a, %b
+ %m2 = fmul contract float %c, %d
+ %a1 = fadd contract contract float %m1, %m2
+ %a2 = fadd contract reassoc float %n0, %a1
ret float %a2
}
@@ -1876,14 +1876,14 @@ define float @fadd_fma_fmul_2(float %a, float %b, float %c, float %d, float %n0)
; AVX512-NEXT: vfmadd231ss {{.*#+}} xmm2 = (xmm1 * xmm0) + xmm2
; AVX512-NEXT: vaddss %xmm2, %xmm4, %xmm0
; AVX512-NEXT: retq
- %m1 = fmul float %a, %b
- %m2 = fmul float %c, %d
- %a1 = fadd contract float %m1, %m2
- %a2 = fadd contract float %n0, %a1
+ %m1 = fmul contract float %a, %b
+ %m2 = fmul contract float %c, %d
+ %a1 = fadd contract contract float %m1, %m2
+ %a2 = fadd contract contract float %n0, %a1
ret float %a2
}
-; The final fadd can be folded with either 1 of the leading fmuls.
+; The final fadd contract can be folded with either 1 of the leading fmul contracts.
define <2 x double> @fadd_fma_fmul_3(<2 x double> %x1, <2 x double> %x2, <2 x double> %x3, <2 x double> %x4, <2 x double> %x5, <2 x double> %x6, <2 x double> %x7, <2 x double> %x8) nounwind {
; FMA-LABEL: fadd_fma_fmul_3:
@@ -1911,13 +1911,13 @@ define <2 x double> @fadd_fma_fmul_3(<2 x double> %x1, <2 x double> %x2, <2 x do
; AVX512-NEXT: vfmadd231pd {{.*#+}} xmm2 = (xmm5 * xmm4) + xmm2
; AVX512-NEXT: vmovapd %xmm2, %xmm0
; AVX512-NEXT: retq
- %m1 = fmul fast <2 x double> %x1, %x2
- %m2 = fmul fast <2 x double> %x3, %x4
- %m3 = fmul fast <2 x double> %x5, %x6
- %m4 = fmul fast <2 x double> %x7, %x8
- %a1 = fadd fast <2 x double> %m1, %m2
- %a2 = fadd fast <2 x double> %m3, %m4
- %a3 = fadd fast <2 x double> %a1, %a2
+ %m1 = fmul contract fast <2 x double> %x1, %x2
+ %m2 = fmul contract fast <2 x double> %x3, %x4
+ %m3 = fmul contract fast <2 x double> %x5, %x6
+ %m4 = fmul contract fast <2 x double> %x7, %x8
+ %a1 = fadd contract fast <2 x double> %m1, %m2
+ %a2 = fadd contract fast <2 x double> %m3, %m4
+ %a3 = fadd contract fast <2 x double> %a1, %a2
ret <2 x double> %a3
}
@@ -1947,11 +1947,11 @@ define float @fadd_fma_fmul_extra_use_1(float %a, float %b, float %c, float %d,
; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm2 = (xmm3 * xmm2) + xmm0
; AVX512-NEXT: vaddss %xmm2, %xmm4, %xmm0
; AVX512-NEXT: retq
- %m1 = fmul fast float %a, %b
+ %m1 = fmul contract fast float %a, %b
store float %m1, ptr %p
- %m2 = fmul fast float %c, %d
- %a1 = fadd fast float %m1, %m2
- %a2 = fadd fast float %n0, %a1
+ %m2 = fmul contract fast float %c, %d
+ %a1 = fadd contract fast float %m1, %m2
+ %a2 = fadd contract fast float %n0, %a1
ret float %a2
}
@@ -1981,11 +1981,11 @@ define float @fadd_fma_fmul_extra_use_2(float %a, float %b, float %c, float %d,
; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
; AVX512-NEXT: vaddss %xmm0, %xmm4, %xmm0
; AVX512-NEXT: retq
- %m1 = fmul fast float %a, %b
- %m2 = fmul fast float %c, %d
+ %m1 = fmul contract fast float %a, %b
+ %m2 = fmul contract fast float %c, %d
store float %m2, ptr %p
- %a1 = fadd fast float %m1, %m2
- %a2 = fadd fast float %n0, %a1
+ %a1 = fadd contract fast float %m1, %m2
+ %a2 = fadd contract fast float %n0, %a1
ret float %a2
}
@@ -2015,10 +2015,10 @@ define float @fadd_fma_fmul_extra_use_3(float %a, float %b, float %c, float %d,
; AVX512-NEXT: vmovss %xmm2, (%rdi)
; AVX512-NEXT: vaddss %xmm2, %xmm4, %xmm0
; AVX512-NEXT: retq
- %m1 = fmul fast float %a, %b
- %m2 = fmul fast float %c, %d
- %a1 = fadd fast float %m1, %m2
+ %m1 = fmul contract fast float %a, %b
+ %m2 = fmul contract fast float %c, %d
+ %a1 = fadd contract fast float %m1, %m2
store float %a1, ptr %p
- %a2 = fadd fast float %n0, %a1
+ %a2 = fadd contract fast float %n0, %a1
ret float %a2
}
diff --git a/llvm/test/CodeGen/X86/fma_patterns_wide.ll b/llvm/test/CodeGen/X86/fma_patterns_wide.ll
index d910110467ee0..4546df5d0255a 100644
--- a/llvm/test/CodeGen/X86/fma_patterns_wide.ll
+++ b/llvm/test/CodeGen/X86/fma_patterns_wide.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma -fp-contract=fast | FileCheck %s --check-prefix=FMA --check-prefix=FMA-INFS
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+fma -fp-contract=fast | FileCheck %s --check-prefix=FMA4 --check-prefix=FMA4-INFS
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4 -fp-contract=fast | FileCheck %s --check-prefix=FMA4 --check-prefix=FMA4-INFS
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq -fp-contract=fast | FileCheck %s --check-prefix=AVX512 --check-prefix=AVX512-INFS
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma -fp-contract=fast -enable-no-infs-fp-math | FileCheck %s --check-prefix=FMA --check-prefix=FMA-NOINFS
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+fma -fp-contract=fast -enable-no-infs-fp-math | FileCheck %s --check-prefix=FMA4 --check-prefix=FMA4-NOINFS
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4 -fp-contract=fast -enable-no-infs-fp-math | FileCheck %s --check-prefix=FMA4 --check-prefix=FMA4-NOINFS
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq -fp-contract=fast -enable-no-infs-fp-math | FileCheck %s --check-prefix=AVX512 --check-prefix=AVX512-NOINFS
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma | FileCheck %s --check-prefix=FMA --check-prefix=FMA-INFS
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+fma | FileCheck %s --check-prefix=FMA4 --check-prefix=FMA4-INFS
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4 | FileCheck %s --check-prefix=FMA4 --check-prefix=FMA4-INFS
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefix=AVX512 --check-prefix=AVX512-INFS
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma -enable-no-infs-fp-math | FileCheck %s --check-prefix=FMA --check-prefix=FMA-NOINFS
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+fma -enable-no-infs-fp-math | FileCheck %s --check-prefix=FMA4 --check-prefix=FMA4-NOINFS
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4 -enable-no-infs-fp-math | FileCheck %s --check-prefix=FMA4 --check-prefix=FMA4-NOINFS
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq -enable-no-infs-fp-math | FileCheck %s --check-prefix=AVX512 --check-prefix=AVX512-NOINFS
;
; Pattern: (fadd (fmul x, y), z) -> (fmadd x,y,z)
@@ -29,8 +29,8 @@ define <16 x float> @test_16f32_fmadd(<16 x float> %a0, <16 x float> %a1, <16 x
; AVX512: # %bb.0:
; AVX512-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; AVX512-NEXT: retq
- %x = fmul <16 x float> %a0, %a1
- %res = fadd <16 x float> %x, %a2
+ %x = fmul contract <16 x float> %a0, %a1
+ %res = fadd contract <16 x float> %x, %a2
ret <16 x float> %res
}
@@ -51,8 +51,8 @@ define <8 x double> @test_8f64_fmadd(<8 x double> %a0, <8 x double> %a1, <8 x do
; AVX512: # %bb.0:
; AVX512-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; AVX512-NEXT: retq
- %x = fmul <8 x double> %a0, %a1
- %res = fadd <8 x double> %x, %a2
+ %x = fmul contract <8 x double> %a0, %a1
+ %res = fadd contract <8 x double> %x, %a2
ret <8 x double> %res
}
@@ -77,8 +77,8 @@ define <16 x float> @test_16f32_fmsub(<16 x float> %a0, <16 x float> %a1, <16 x
; AVX512: # %bb.0:
; AVX512-NEXT: vfmsub213ps {{.*#+}} zmm0 = (zmm1 * zmm0) - zmm2
; AVX512-NEXT: retq
- %x = fmul <16 x float> %a0, %a1
- %res = fsub <16 x float> %x, %a2
+ %x = fmul contract <16 x float> %a0, %a1
+ %res = fsub contract <16 x float> %x, %a2
ret <16 x float> %res
}
@@ -99,8 +99,8 @@ define <8 x double> @test_8f64_fmsub(<8 x double> %a0, <8 x double> %a1, <8 x do
; AVX512: # %bb.0:
; AVX512-NEXT: vfmsub213pd {{.*#+}} zmm0 = (zmm1 * zmm0) - zmm2
; AVX512-NEXT: retq
- %x = fmul <8 x double> %a0, %a1
- %res = fsub <8 x double> %x, %a2
+ %x = fmul contract <8 x double> %a0, %a1
+ %res = fsub contract <8 x double> %x, %a2
ret <8 x double> %res
}
@@ -125,8 +125,8 @@ define <16 x float> @test_16f32_fnmadd(<16 x float> %a0, <16 x float> %a1, <16 x
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmadd213ps {{.*#+}} zmm0 = -(zmm1 * zmm0) + zmm2
; AVX512-NEXT: retq
- %x = fmul <16 x float> %a0, %a1
- %res = fsub <16 x float> %a2, %x
+ %x = fmul contract <16 x float> %a0, %a1
+ %res = fsub contract <16 x float> %a2, %x
ret <16 x float> %res
}
@@ -147,8 +147,8 @@ define <8 x double> @test_8f64_fnmadd(<8 x double> %a0, <8 x double> %a1, <8 x d
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmadd213pd {{.*#+}} zmm0 = -(zmm1 * zmm0) + zmm2
; AVX512-NEXT: retq
- %x = fmul <8 x double> %a0, %a1
- %res = fsub <8 x double> %a2, %x
+ %x = fmul contract <8 x double> %a0, %a1
+ %res = fsub contract <8 x double> %a2, %x
ret <8 x double> %res
}
@@ -173,9 +173,9 @@ define <16 x float> @test_16f32_fnmsub(<16 x float> %a0, <16 x float> %a1, <16 x
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmsub213ps {{.*#+}} zmm0 = -(zmm1 * zmm0) - zmm2
; AVX512-NEXT: retq
- %x = fmul <16 x float> %a0, %a1
- %y = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x
- %res = fsub <16 x float> %y, %a2
+ %x = fmul contract <16 x float> %a0, %a1
+ %y = fsub contract <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x
+ %res = fsub contract <16 x float> %y, %a2
ret <16 x float> %res
}
@@ -196,9 +196,9 @@ define <8 x double> @test_8f64_fnmsub(<8 x double> %a0, <8 x double> %a1, <8 x d
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmsub213pd {{.*#+}} zmm0 = -(zmm1 * zmm0) - zmm2
; AVX512-NEXT: retq
- %x = fmul <8 x double> %a0, %a1
- %y = fsub <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %x
- %res = fsub <8 x double> %y, %a2
+ %x = fmul contract <8 x double> %a0, %a1
+ %y = fsub contract <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %x
+ %res = fsub contract <8 x double> %y, %a2
ret <8 x double> %res
}
@@ -224,8 +224,8 @@ define <16 x float> @test_16f32_fmadd_load(ptr %a0, <16 x float> %a1, <16 x floa
; AVX512-NEXT: vfmadd132ps {{.*#+}} zmm0 = (zmm0 * mem) + zmm1
; AVX512-NEXT: retq
%x = load <16 x float>, ptr %a0
- %y = fmul <16 x float> %x, %a1
- %res = fadd <16 x float> %y, %a2
+ %y = fmul contract <16 x float> %x, %a1
+ %res = fadd contract <16 x float> %y, %a2
ret <16 x float> %res
}
@@ -247,8 +247,8 @@ define <8 x double> @test_8f64_fmsub_load(ptr %a0, <8 x double> %a1, <8 x double
; AVX512-NEXT: vfmsub132pd {{.*#+}} zmm0 = (zmm0 * mem) - zmm1
; AVX512-NEXT: retq
%x = load <8 x double>, ptr %a0
- %y = fmul <8 x double> %x, %a1
- %res = fsub <8 x double> %y, %a2
+ %y = fmul contract <8 x double> %x, %a1
+ %res = fsub contract <8 x double> %y, %a2
ret <8 x double> %res
}
@@ -297,8 +297,8 @@ define <16 x float> @test_v16f32_mul_add_x_one_y(<16 x float> %x, <16 x float> %
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm1
; AVX512-NOINFS-NEXT: retq
- %a = fadd <16 x float> %x, <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>
- %m = fmul <16 x float> %a, %y
+ %a = fadd contract <16 x float> %x, <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>
+ %m = fmul contract <16 x float> %a, %y
ret <16 x float> %m
}
@@ -343,8 +343,8 @@ define <8 x double> @test_v8f64_mul_y_add_x_one(<8 x double> %x, <8 x double> %y
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm1
; AVX512-NOINFS-NEXT: retq
- %a = fadd <8 x double> %x, <double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0>
- %m = fmul <8 x double> %y, %a
+ %a = fadd contract <8 x double> %x, <double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0>
+ %m = fmul contract <8 x double> %y, %a
ret <8 x double> %m
}
@@ -389,8 +389,8 @@ define <16 x float> @test_v16f32_mul_add_x_negone_y(<16 x float> %x, <16 x float
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmsub213ps {{.*#+}} zmm0 = (zmm1 * zmm0) - zmm1
; AVX512-NOINFS-NEXT: retq
- %a = fadd <16 x float> %x, <float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0>
- %m = fmul <16 x float> %a, %y
+ %a = fadd contract <16 x float> %x, <float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0>
+ %m = fmul contract <16 x float> %a, %y
ret <16 x float> %m
}
@@ -435,8 +435,8 @@ define <8 x double> @test_v8f64_mul_y_add_x_negone(<8 x double> %x, <8 x double>
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmsub213pd {{.*#+}} zmm0 = (zmm1 * zmm0) - zmm1
; AVX512-NOINFS-NEXT: retq
- %a = fadd <8 x double> %x, <double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0>
- %m = fmul <8 x double> %y, %a
+ %a = fadd contract <8 x double> %x, <double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0>
+ %m = fmul contract <8 x double> %y, %a
ret <8 x double> %m
}
@@ -482,8 +482,8 @@ define <16 x float> @test_v16f32_mul_sub_one_x_y(<16 x float> %x, <16 x float> %
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfnmadd213ps {{.*#+}} zmm0 = -(zmm1 * zmm0) + zmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <16 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %x
- %m = fmul <16 x float> %s, %y
+ %s = fsub contract <16 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %x
+ %m = fmul contract <16 x float> %s, %y
ret <16 x float> %m
}
@@ -529,8 +529,8 @@ define <8 x double> @test_v8f64_mul_y_sub_one_x(<8 x double> %x, <8 x double> %y
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfnmadd213pd {{.*#+}} zmm0 = -(zmm1 * zmm0) + zmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <8 x double> <double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0>, %x
- %m = fmul <8 x double> %y, %s
+ %s = fsub contract <8 x double> <double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0>, %x
+ %m = fmul contract <8 x double> %y, %s
ret <8 x double> %m
}
@@ -576,8 +576,8 @@ define <16 x float> @test_v16f32_mul_sub_negone_x_y(<16 x float> %x, <16 x float
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfnmsub213ps {{.*#+}} zmm0 = -(zmm1 * zmm0) - zmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <16 x float> <float -1.0, float -1.0, float -1.0, float -1.0,float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0>, %x
- %m = fmul <16 x float> %s, %y
+ %s = fsub contract <16 x float> <float -1.0, float -1.0, float -1.0, float -1.0,float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0>, %x
+ %m = fmul contract <16 x float> %s, %y
ret <16 x float> %m
}
@@ -623,8 +623,8 @@ define <8 x double> @test_v8f64_mul_y_sub_negone_x(<8 x double> %x, <8 x double>
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfnmsub213pd {{.*#+}} zmm0 = -(zmm1 * zmm0) - zmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <8 x double> <double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0>, %x
- %m = fmul <8 x double> %y, %s
+ %s = fsub contract <8 x double> <double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0>, %x
+ %m = fmul contract <8 x double> %y, %s
ret <8 x double> %m
}
@@ -669,8 +669,8 @@ define <16 x float> @test_v16f32_mul_sub_x_one_y(<16 x float> %x, <16 x float> %
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmsub213ps {{.*#+}} zmm0 = (zmm1 * zmm0) - zmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <16 x float> %x, <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>
- %m = fmul <16 x float> %s, %y
+ %s = fsub contract <16 x float> %x, <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>
+ %m = fmul contract <16 x float> %s, %y
ret <16 x float> %m
}
@@ -715,8 +715,8 @@ define <8 x double> @test_v8f64_mul_y_sub_x_one(<8 x double> %x, <8 x double> %y
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmsub213pd {{.*#+}} zmm0 = (zmm1 * zmm0) - zmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <8 x double> %x, <double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0>
- %m = fmul <8 x double> %y, %s
+ %s = fsub contract <8 x double> %x, <double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0>
+ %m = fmul contract <8 x double> %y, %s
ret <8 x double> %m
}
@@ -761,8 +761,8 @@ define <16 x float> @test_v16f32_mul_sub_x_negone_y(<16 x float> %x, <16 x float
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <16 x float> %x, <float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0>
- %m = fmul <16 x float> %s, %y
+ %s = fsub contract <16 x float> %x, <float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0, float -1.0>
+ %m = fmul contract <16 x float> %s, %y
ret <16 x float> %m
}
@@ -807,8 +807,8 @@ define <8 x double> @test_v8f64_mul_y_sub_x_negone(<8 x double> %x, <8 x double>
; AVX512-NOINFS: # %bb.0:
; AVX512-NOINFS-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm1
; AVX512-NOINFS-NEXT: retq
- %s = fsub <8 x double> %x, <double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0>
- %m = fmul <8 x double> %y, %s
+ %s = fsub contract <8 x double> %x, <double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0>
+ %m = fmul contract <8 x double> %y, %s
ret <8 x double> %m
}
@@ -868,10 +868,10 @@ define <16 x float> @test_v16f32_interp(<16 x float> %x, <16 x float> %y, <16 x
; AVX512-NOINFS-NEXT: vfmsub213ps {{.*#+}} zmm1 = (zmm2 * zmm1) - zmm1
; AVX512-NOINFS-NEXT: vfmsub213ps {{.*#+}} zmm0 = (zmm2 * zmm0) - zmm1
; AVX512-NOINFS-NEXT: retq
- %t1 = fsub nsz <16 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %t
- %tx = fmul nsz <16 x float> %x, %t
- %ty = fmul nsz <16 x float> %y, %t1
- %r = fadd nsz <16 x float> %tx, %ty
+ %t1 = fsub contract nsz <16 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %t
+ %tx = fmul contract nsz <16 x float> %x, %t
+ %ty = fmul contract nsz <16 x float> %y, %t1
+ %r = fadd contract nsz <16 x float> %tx, %ty
ret <16 x float> %r
}
@@ -927,10 +927,10 @@ define <8 x double> @test_v8f64_interp(<8 x double> %x, <8 x double> %y, <8 x do
; AVX512-NOINFS-NEXT: vfmsub213pd {{.*#+}} zmm1 = (zmm2 * zmm1) - zmm1
; AVX512-NOINFS-NEXT: vfmsub213pd {{.*#+}} zmm0 = (zmm2 * zmm0) - zmm1
; AVX512-NOINFS-NEXT: retq
- %t1 = fsub nsz <8 x double> <double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0>, %t
- %tx = fmul nsz <8 x double> %x, %t
- %ty = fmul nsz <8 x double> %y, %t1
- %r = fadd nsz <8 x double> %tx, %ty
+ %t1 = fsub contract nsz <8 x double> <double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0, double 1.0>, %t
+ %tx = fmul contract nsz <8 x double> %x, %t
+ %ty = fmul contract nsz <8 x double> %y, %t1
+ %r = fadd contract nsz <8 x double> %tx, %ty
ret <8 x double> %r
}
@@ -955,9 +955,9 @@ define <16 x float> @test_v16f32_fneg_fmadd(<16 x float> %a0, <16 x float> %a1,
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmsub213ps {{.*#+}} zmm0 = -(zmm1 * zmm0) - zmm2
; AVX512-NEXT: retq
- %mul = fmul nsz <16 x float> %a0, %a1
- %add = fadd nsz <16 x float> %mul, %a2
- %neg = fsub nsz <16 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, %add
+ %mul = fmul contract nsz <16 x float> %a0, %a1
+ %add = fadd contract nsz <16 x float> %mul, %a2
+ %neg = fsub contract nsz <16 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, %add
ret <16 x float> %neg
}
@@ -978,9 +978,9 @@ define <8 x double> @test_v8f64_fneg_fmsub(<8 x double> %a0, <8 x double> %a1, <
; AVX512: # %bb.0:
; AVX512-NEXT: vfnmadd213pd {{.*#+}} zmm0 = -(zmm1 * zmm0) + zmm2
; AVX512-NEXT: retq
- %mul = fmul nsz <8 x double> %a0, %a1
- %sub = fsub nsz <8 x double> %mul, %a2
- %neg = fsub nsz <8 x double> <double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0>, %sub
+ %mul = fmul contract nsz <8 x double> %a0, %a1
+ %sub = fsub contract nsz <8 x double> %mul, %a2
+ %neg = fsub contract nsz <8 x double> <double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0>, %sub
ret <8 x double> %neg
}
@@ -1001,10 +1001,10 @@ define <16 x float> @test_v16f32_fneg_fnmadd(<16 x float> %a0, <16 x float> %a1,
; AVX512: # %bb.0:
; AVX512-NEXT: vfmsub213ps {{.*#+}} zmm0 = (zmm1 * zmm0) - zmm2
; AVX512-NEXT: retq
- %mul = fmul nsz <16 x float> %a0, %a1
- %neg0 = fsub nsz <16 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, %mul
- %add = fadd nsz <16 x float> %neg0, %a2
- %neg1 = fsub nsz <16 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, %add
+ %mul = fmul contract nsz <16 x float> %a0, %a1
+ %neg0 = fsub contract nsz <16 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, %mul
+ %add = fadd contract nsz <16 x float> %neg0, %a2
+ %neg1 = fsub contract nsz <16 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, %add
ret <16 x float> %neg1
}
@@ -1025,10 +1025,10 @@ define <8 x double> @test_v8f64_fneg_fnmsub(<8 x double> %a0, <8 x double> %a1,
; AVX512: # %bb.0:
; AVX512-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; AVX512-NEXT: retq
- %mul = fmul nsz <8 x double> %a0, %a1
- %neg0 = fsub nsz <8 x double> <double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0>, %mul
- %sub = fsub nsz <8 x double> %neg0, %a2
- %neg1 = fsub nsz <8 x double> <double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0>, %sub
+ %mul = fmul contract nsz <8 x double> %a0, %a1
+ %neg0 = fsub contract nsz <8 x double> <double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0>, %mul
+ %sub = fsub contract nsz <8 x double> %neg0, %a2
+ %neg1 = fsub contract nsz <8 x double> <double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0>, %sub
ret <8 x double> %neg1
}
@@ -1108,8 +1108,8 @@ define <16 x float> @test_v16f32_fneg_fmul(<16 x float> %x, <16 x float> %y) #0
; AVX512-NEXT: vxorps %xmm2, %xmm2, %xmm2
; AVX512-NEXT: vfnmsub213ps {{.*#+}} zmm0 = -(zmm1 * zmm0) - zmm2
; AVX512-NEXT: retq
- %m = fmul nsz <16 x float> %x, %y
- %n = fsub <16 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, %m
+ %m = fmul contract nsz <16 x float> %x, %y
+ %n = fsub contract <16 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, %m
ret <16 x float> %n
}
@@ -1133,8 +1133,8 @@ define <8 x double> @test_v8f64_fneg_fmul(<8 x double> %x, <8 x double> %y) #0 {
; AVX512-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; AVX512-NEXT: vfnmsub213pd {{.*#+}} zmm0 = -(zmm1 * zmm0) - zmm2
; AVX512-NEXT: retq
- %m = fmul nsz <8 x double> %x, %y
- %n = fsub <8 x double> <double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0>, %m
+ %m = fmul contract nsz <8 x double> %x, %y
+ %n = fsub contract <8 x double> <double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0>, %m
ret <8 x double> %n
}
@@ -1162,8 +1162,8 @@ define <8 x double> @test_v8f64_fneg_fmul_no_nsz(<8 x double> %x, <8 x double> %
; AVX512-NEXT: vmulpd %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; AVX512-NEXT: retq
- %m = fmul <8 x double> %x, %y
- %n = fsub <8 x double> <double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0>, %m
+ %m = fmul contract <8 x double> %x, %y
+ %n = fsub contract <8 x double> <double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0>, %m
ret <8 x double> %n
}
diff --git a/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll b/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
index d59b12c6d1231..d8c8b1c646c7c 100644
--- a/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
+++ b/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=CHECK-SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK-AVX,CHECK-AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK-AVX,CHECK-AVX512F,CHECK-NO-FASTFMA
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx -fp-contract=fast | FileCheck %s --check-prefixes=CHECK-AVX,CHECK-AVX512F,CHECK-FMA
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s --check-prefixes=CHECK-AVX,CHECK-AVX512F,CHECK-FMA
declare i16 @llvm.umax.i16(i16, i16)
declare i64 @llvm.umin.i64(i64, i64)
@@ -1007,14 +1007,6 @@ define <4 x float> @fmul_pow_shl_cnt_vec_preserve_fma(<4 x i32> %cnt, <4 x float
; CHECK-AVX2-NEXT: vaddps %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq
;
-; CHECK-NO-FASTFMA-LABEL: fmul_pow_shl_cnt_vec_preserve_fma:
-; CHECK-NO-FASTFMA: # %bb.0:
-; CHECK-NO-FASTFMA-NEXT: vpslld $23, %xmm0, %xmm0
-; CHECK-NO-FASTFMA-NEXT: vpbroadcastd {{.*#+}} xmm2 = [1092616192,1092616192,1092616192,1092616192]
-; CHECK-NO-FASTFMA-NEXT: vpaddd %xmm2, %xmm0, %xmm0
-; CHECK-NO-FASTFMA-NEXT: vaddps %xmm1, %xmm0, %xmm0
-; CHECK-NO-FASTFMA-NEXT: retq
-;
; CHECK-FMA-LABEL: fmul_pow_shl_cnt_vec_preserve_fma:
; CHECK-FMA: # %bb.0:
; CHECK-FMA-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2,2,2,2]
@@ -1024,8 +1016,8 @@ define <4 x float> @fmul_pow_shl_cnt_vec_preserve_fma(<4 x i32> %cnt, <4 x float
; CHECK-FMA-NEXT: retq
%shl = shl nsw nuw <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %cnt
%conv = uitofp <4 x i32> %shl to <4 x float>
- %mul = fmul <4 x float> <float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00>, %conv
- %res = fadd <4 x float> %mul, %add
+ %mul = fmul contract <4 x float> <float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00>, %conv
+ %res = fadd contract <4 x float> %mul, %add
ret <4 x float> %res
}
diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll b/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll
index 42617c1573be5..417910df5c457 100644
--- a/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll
+++ b/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -fp-contract=fast < %s -mtriple=x86_64-unknown-unknown -mattr=avx2,fma -stop-after=finalize-isel 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2,fma -stop-after=finalize-isel 2>&1 | FileCheck %s
declare float @llvm.sqrt.f32(float) #2
@@ -10,10 +10,10 @@ define float @sqrt_ieee(float %f) #0 {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
; CHECK-NEXT: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
- ; CHECK-NEXT: [[VSQRTSSr:%[0-9]+]]:fr32 = nofpexcept VSQRTSSr killed [[DEF]], [[COPY]], implicit $mxcsr
+ ; CHECK-NEXT: [[VSQRTSSr:%[0-9]+]]:fr32 = contract nofpexcept VSQRTSSr killed [[DEF]], [[COPY]], implicit $mxcsr
; CHECK-NEXT: $xmm0 = COPY [[VSQRTSSr]]
; CHECK-NEXT: RET 0, $xmm0
- %call = tail call float @llvm.sqrt.f32(float %f)
+ %call = tail call contract float @llvm.sqrt.f32(float %f)
ret float %call
}
@@ -25,16 +25,16 @@ define float @sqrt_ieee_ninf(float %f) #0 {
; CHECK-NEXT: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
; CHECK-NEXT: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
; CHECK-NEXT: [[VRSQRTSSr:%[0-9]+]]:fr32 = VRSQRTSSr killed [[DEF]], [[COPY]]
- ; CHECK-NEXT: [[VMULSSrr:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[COPY]], [[VRSQRTSSr]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr [[COPY]], [[VRSQRTSSr]], implicit $mxcsr
; CHECK-NEXT: [[VMOVSSrm_alt:%[0-9]+]]:fr32 = VMOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load (s32) from constant-pool)
- ; CHECK-NEXT: [[VFMADD213SSr:%[0-9]+]]:fr32 = ninf afn nofpexcept VFMADD213SSr [[VRSQRTSSr]], killed [[VMULSSrr]], [[VMOVSSrm_alt]], implicit $mxcsr
+ ; CHECK-NEXT: [[VFMADD213SSr:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VFMADD213SSr [[VRSQRTSSr]], killed [[VMULSSrr]], [[VMOVSSrm_alt]], implicit $mxcsr
; CHECK-NEXT: [[VMOVSSrm_alt1:%[0-9]+]]:fr32 = VMOVSSrm_alt $rip, 1, $noreg, %const.1, $noreg :: (load (s32) from constant-pool)
- ; CHECK-NEXT: [[VMULSSrr1:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[VRSQRTSSr]], [[VMOVSSrm_alt1]], implicit $mxcsr
- ; CHECK-NEXT: [[VMULSSrr2:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr killed [[VMULSSrr1]], killed [[VFMADD213SSr]], implicit $mxcsr
- ; CHECK-NEXT: [[VMULSSrr3:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[COPY]], [[VMULSSrr2]], implicit $mxcsr
- ; CHECK-NEXT: [[VFMADD213SSr1:%[0-9]+]]:fr32 = ninf afn nofpexcept VFMADD213SSr [[VMULSSrr2]], [[VMULSSrr3]], [[VMOVSSrm_alt]], implicit $mxcsr
- ; CHECK-NEXT: [[VMULSSrr4:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[VMULSSrr3]], [[VMOVSSrm_alt1]], implicit $mxcsr
- ; CHECK-NEXT: [[VMULSSrr5:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr killed [[VMULSSrr4]], killed [[VFMADD213SSr1]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr1:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr [[VRSQRTSSr]], [[VMOVSSrm_alt1]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr2:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr killed [[VMULSSrr1]], killed [[VFMADD213SSr]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr3:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr [[COPY]], [[VMULSSrr2]], implicit $mxcsr
+ ; CHECK-NEXT: [[VFMADD213SSr1:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VFMADD213SSr [[VMULSSrr2]], [[VMULSSrr3]], [[VMOVSSrm_alt]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr4:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr [[VMULSSrr3]], [[VMOVSSrm_alt1]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr5:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr killed [[VMULSSrr4]], killed [[VFMADD213SSr1]], implicit $mxcsr
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY killed [[VMULSSrr5]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY]]
; CHECK-NEXT: [[VPBROADCASTDrm:%[0-9]+]]:vr128 = VPBROADCASTDrm $rip, 1, $noreg, %const.2, $noreg :: (load (s32) from constant-pool)
@@ -46,7 +46,7 @@ define float @sqrt_ieee_ninf(float %f) #0 {
; CHECK-NEXT: [[COPY5:%[0-9]+]]:fr32 = COPY killed [[VPANDNrr]]
; CHECK-NEXT: $xmm0 = COPY [[COPY5]]
; CHECK-NEXT: RET 0, $xmm0
- %call = tail call ninf afn float @llvm.sqrt.f32(float %f)
+ %call = tail call contract ninf afn contract float @llvm.sqrt.f32(float %f)
ret float %call
}
@@ -57,10 +57,10 @@ define float @sqrt_daz(float %f) #1 {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
; CHECK-NEXT: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
- ; CHECK-NEXT: [[VSQRTSSr:%[0-9]+]]:fr32 = nofpexcept VSQRTSSr killed [[DEF]], [[COPY]], implicit $mxcsr
+ ; CHECK-NEXT: [[VSQRTSSr:%[0-9]+]]:fr32 = contract nofpexcept VSQRTSSr killed [[DEF]], [[COPY]], implicit $mxcsr
; CHECK-NEXT: $xmm0 = COPY [[VSQRTSSr]]
; CHECK-NEXT: RET 0, $xmm0
- %call = tail call float @llvm.sqrt.f32(float %f)
+ %call = tail call contract float @llvm.sqrt.f32(float %f)
ret float %call
}
@@ -72,16 +72,16 @@ define float @sqrt_daz_ninf(float %f) #1 {
; CHECK-NEXT: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
; CHECK-NEXT: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
; CHECK-NEXT: [[VRSQRTSSr:%[0-9]+]]:fr32 = VRSQRTSSr killed [[DEF]], [[COPY]]
- ; CHECK-NEXT: [[VMULSSrr:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[COPY]], [[VRSQRTSSr]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr [[COPY]], [[VRSQRTSSr]], implicit $mxcsr
; CHECK-NEXT: [[VMOVSSrm_alt:%[0-9]+]]:fr32 = VMOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load (s32) from constant-pool)
- ; CHECK-NEXT: [[VFMADD213SSr:%[0-9]+]]:fr32 = ninf afn nofpexcept VFMADD213SSr [[VRSQRTSSr]], killed [[VMULSSrr]], [[VMOVSSrm_alt]], implicit $mxcsr
+ ; CHECK-NEXT: [[VFMADD213SSr:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VFMADD213SSr [[VRSQRTSSr]], killed [[VMULSSrr]], [[VMOVSSrm_alt]], implicit $mxcsr
; CHECK-NEXT: [[VMOVSSrm_alt1:%[0-9]+]]:fr32 = VMOVSSrm_alt $rip, 1, $noreg, %const.1, $noreg :: (load (s32) from constant-pool)
- ; CHECK-NEXT: [[VMULSSrr1:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[VRSQRTSSr]], [[VMOVSSrm_alt1]], implicit $mxcsr
- ; CHECK-NEXT: [[VMULSSrr2:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr killed [[VMULSSrr1]], killed [[VFMADD213SSr]], implicit $mxcsr
- ; CHECK-NEXT: [[VMULSSrr3:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[COPY]], [[VMULSSrr2]], implicit $mxcsr
- ; CHECK-NEXT: [[VFMADD213SSr1:%[0-9]+]]:fr32 = ninf afn nofpexcept VFMADD213SSr [[VMULSSrr2]], [[VMULSSrr3]], [[VMOVSSrm_alt]], implicit $mxcsr
- ; CHECK-NEXT: [[VMULSSrr4:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[VMULSSrr3]], [[VMOVSSrm_alt1]], implicit $mxcsr
- ; CHECK-NEXT: [[VMULSSrr5:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr killed [[VMULSSrr4]], killed [[VFMADD213SSr1]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr1:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr [[VRSQRTSSr]], [[VMOVSSrm_alt1]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr2:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr killed [[VMULSSrr1]], killed [[VFMADD213SSr]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr3:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr [[COPY]], [[VMULSSrr2]], implicit $mxcsr
+ ; CHECK-NEXT: [[VFMADD213SSr1:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VFMADD213SSr [[VMULSSrr2]], [[VMULSSrr3]], [[VMOVSSrm_alt]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr4:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr [[VMULSSrr3]], [[VMOVSSrm_alt1]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr5:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr killed [[VMULSSrr4]], killed [[VFMADD213SSr1]], implicit $mxcsr
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY killed [[VMULSSrr5]]
; CHECK-NEXT: [[FsFLD0SS:%[0-9]+]]:fr32 = FsFLD0SS
; CHECK-NEXT: [[VCMPSSrri:%[0-9]+]]:fr32 = nofpexcept VCMPSSrri [[COPY]], killed [[FsFLD0SS]], 0, implicit $mxcsr
@@ -90,7 +90,7 @@ define float @sqrt_daz_ninf(float %f) #1 {
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fr32 = COPY killed [[VPANDNrr]]
; CHECK-NEXT: $xmm0 = COPY [[COPY3]]
; CHECK-NEXT: RET 0, $xmm0
- %call = tail call ninf afn float @llvm.sqrt.f32(float %f)
+ %call = tail call contract ninf afn float @llvm.sqrt.f32(float %f)
ret float %call
}
@@ -114,7 +114,7 @@ define float @rsqrt_ieee(float %f) #0 {
; CHECK-NEXT: [[VMULSSrr5:%[0-9]+]]:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed [[VMULSSrr4]], killed [[VFMADD213SSr1]], implicit $mxcsr
; CHECK-NEXT: $xmm0 = COPY [[VMULSSrr5]]
; CHECK-NEXT: RET 0, $xmm0
- %sqrt = tail call float @llvm.sqrt.f32(float %f)
+ %sqrt = tail call contract float @llvm.sqrt.f32(float %f)
%div = fdiv fast float 1.0, %sqrt
ret float %div
}
@@ -139,7 +139,7 @@ define float @rsqrt_daz(float %f) #1 {
; CHECK-NEXT: [[VMULSSrr5:%[0-9]+]]:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed [[VMULSSrr4]], killed [[VFMADD213SSr1]], implicit $mxcsr
; CHECK-NEXT: $xmm0 = COPY [[VMULSSrr5]]
; CHECK-NEXT: RET 0, $xmm0
- %sqrt = tail call float @llvm.sqrt.f32(float %f)
+ %sqrt = tail call contract float @llvm.sqrt.f32(float %f)
%div = fdiv fast float 1.0, %sqrt
ret float %div
}
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