[llvm] [VPlan] Always consider register pressure on RISC-V (PR #156951)

[Elvis Wang via llvm-commits]

ElvisWang123 wrote:


> > AArch64 has a lot more registers so is less susceptible to spilling, it is often still beneficial to vectorizer, and scalar often spills in around the same amount I suspect. It might be better if it was accounted for in the cost of the vplans (both scalar and vector), not a straight prevention of any vectorization.

> Agreed, I think we can probably do a very rough estimate of the spill cost with TTI.getMemoryOpCost. And if we can also compute the register pressure on the scalar VPlan and add the spill cost to that we would hopefully get a better idea of when vectorizing is profitable in the face of spilling

Agreed too. We have some similar implementation (accounting costs for vector register spill and reload) in the downstream and it works quite well.  Would be good to have this feature in upstream in future.




https://github.com/llvm/llvm-project/pull/156951